Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 14

Summary Table of Changes
Errata (Sheet 2 of 5)
D-0/ E-0/
No.
0F34h 0F41h 0F49h
S20 X
S21 X X
S22
S23 X X
S24 X X
S25 X X
S26 X X
S27 X
S28 X X
S29 X X
S30 X X
S31 X X
S32 X X
S33
S34 X X
S35 X X
S36 X X
S37 X X
S38 X X
S39 X
S40 X
S41 X
S42 X
14
G-1/ N-0/ R-0/
Plans
0F43h 0F4Ah
Fixed
X X X No Fix
Fixed
X X X No Fix
X X X No Fix
X X X Plan Fix
X X X Plan Fix
X X X No Fix
X Fixed
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X Plan Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
Fixed
Fixed
Fixed
Fixed
A 16-bit address wrap resulting from a near branch (jump or
call) may cause an incorrect address to be reported to the
#GP exception handler
Bus locks and SMC detection may cause the processor to
temporarily hang
Incorrect physical address size returned by CPUID instruction
Incorrect debug exception (#DB) may occur when a data
breakpoint is set on an FP instruction
xAPIC may not report some illegal vector errors
Enabling no-eviction mode (NEM) may prevent the operation
of the second logical processor in a Hyper-Threading
Technology enabled boot strap processor (BSP)
TPR (Task Priority Register) updates during voltage
transitions of power management events may cause a system
hang
Interactions between the instruction translation lookaside
buffer (ITLB) and the instruction streaming buffer may cause
unpredictable software behavior
STPCLK# signal assertion under certain conditions may
cause a system hang
Incorrect duty cycle is chosen when on-demand clock
modulation is enabled in a processor supporting
Hyper-Threading Technology
Memory aliasing of pages as uncacheable memory type and
write back (WB) may hang the system
Using STPCLK# and executing code from very slow memory
could lead to a system hang
Processor provides a 4-byte store unlock after an 8-byte load
lock
Duplicate Erratum: see S5
Execution of IRET and INTn instructions may cause
unexpected system behavior
Data breakpoints on the high half of a floating-point line split
may not be captured
Machine Check Exceptions may not update Last-Exception
Record MSRs (LERs)
MOV CR3 performs incorrect reserved bit checking when in
PAE paging
Stores to page tables may not be visible to pagewalks for
subsequent loads without serializing or invalidating the page
table entry
A split store memory access may miss a data breakpoint
EFLAGS.RF may be incorrectly set after an IRET instruction
Writing the Echo TPR disable bit in IA32_MISC_ENABLE
may cause a #GP fault
Incorrect access controls to
MSR_LASTBRANCH_0_FROM_LIP MSR registers
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata