Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 16

Summary Table of Changes
Errata (Sheet 4 of 5)
D-0/ E-0/
No.
0F34h 0F41h 0F49h
S63 X
S64 X
S65 X
S66 X X
S67 X X
S68 X X
S69 X X
S70 X
S71 X X
S72 X
S73 X X
S74
S75 X X
S76 X X
S77 X X
S78 X X
S79 X X
S80 X X
16
G-1/ N-0/ R-0/
Plans
0F43h 0F4Ah
Fixed
Fixed
Fixed
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
Fixed
X X X No Fix
X X Fixed
X X Fixed
X Fixed
X X X No Fix
X X X No Fix
X X X No Fix
X X Fixed
X X X Plan Fix
X X Fixed
Writes to IA32_MISC_ENABLE may not update flags for both
logical processors
Execute Disable Bit set with CR4.PAE may cause livelock
SYSENTER or SYSEXIT instructions may experience
incorrect canonical address checking on processors
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
Checking of Page Table Base Address may not match
Address Bit Width supported by the platform
IA32_MCi_STATUS MSR may improperly indicate that
additional MCA information may have been captured
With Trap Flag (TF) asserted, FP instruction that triggers
unmasked FP Exception may take single step trap before
retirement of instruction
PDE/PTE loads and continuous locked updates to the same
cache line may cause system livelock
MCA-corrected memory hierarchy error counter may not
increment correctly
Branch Trace Store (BTS) and Precise Event-Based
Sampling (PEBS) may update memory outside the
BTS/PEBS buffer
L-bit of CS and LMA bit of IA32_EFER register may have
erroneous value for one instruction following mode transition
in Hyper-Threading Technology-Enabled processor
supporting Intel® Extended Memory 64 Technology (Intel®
EM64T)
The base of an LDT (Local Descriptor Table) register may be
non-zero on a processor supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
Unaligned Page-Directory-Pointer (PDPTR) Base with 32-bit
mode PAE (Page Address Extension) paging may cause
processor to hang
Memory ordering failure may occur with snoop filtering
third-party agents after issuing and completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) transaction
Control Register 2 (CR2) can be updated during a REP
MOVS/STOS instruction with fast strings enabled
REP STOS/MOVS instructions with RCX >= 2^32 may cause
system hang
REP MOVS or REP STOS instruction with RCX >= 2^32 may
fail to execute to completion or may write to incorrect memory
locations on processors supporting Intel® Extended Memory
64 Technology (Intel® EM64T)
An REP LODSB or an REP LODSD or an REP LODSQ
instruction with RCX >= 2^32 may cause a system hang on
processors supporting Intel® Extended Memory 64
Technology (Intel® EM64T)
Data access which spans both canonical and non-canonical
address space may hang system
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata