Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 32

Errata
S48 The base of a null segment may be non-zero on a processor supporting
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Intel Extended Memory 64 Technology (Intel
Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero.
Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when
accessing memory using the null selector.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S49 Upper 32 bits of FS/GS with null base may not get cleared in Virtual-8086
Mode on processors with Intel
EM64T) Enabled
Problem: For processors with Intel EM64T enabled, the upper 32 bits of the FS and GS data segment
registers corresponding to a null base may not get cleared when segments are loaded in
Virtual-8086 mode.
Implication: This erratum may cause incorrect data to be loaded or stored to memory if FS/GS is not initialized
before use in 64-bit mode. Intel has not observed this erratum with any commercially available
software.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S50 Processor may fault when the upper 8 bytes of segment selector is loaded
from a far jump through a call gate via the Local Descriptor Table
In IA-32e mode of the Intel EM64T processor, control transfers through a call gate via the Local
Problem:
Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and
access an incorrect descriptor in the LDT. This only occurs on an LDT with a LIMIT>0x10008
with a 16-byte descriptor that has a selector of 0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an incorrect
descriptor within the LDT, potentially resulting in a fault or system hang. Intel has not observed
this erratum with any commercially available software.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S51 Compatibility mode STOS instructions may alter RSI register results on a
processor supporting Intel
EM64T)
When a processor supporting Intel EM64T is in IA-32e mode and executes a STOS instruction in
Problem:
compatibility mode, it may modify the RSI register contents.
Implication: When this erratum occurs, systems may encounter unexpected behavior.
It is possible for the BIOS to contain a workaround for this erratum.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S52 LDT descriptor which crosses 16 bit boundary access does not cause a
#GP fault on a processor supporting Intel
Technology (Intel
When a processor supporting Intel EM64T in IA-32e mode accesses an LDT entry (16-byte) that
Problem:
crosses the 0xffff limit, a #GP fault is not signaled and instead the upper 8-bytes of the entry is
fetched from the wrapped around address (usually 0x0). This will cause the erroneous data to be
loaded into the upper 8-bytes of the descriptor.
32
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Extended Memory 64 Technology (Intel
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Extended Memory 64 Technology (Intel
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EM64T)
64-bit Intel
(1 MB and 2 MB L2 Cache Versions) Specification Update
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EM64T)
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Extended Memory 64
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Xeon Processor with 800 MHz System Bus
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