Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 13

W = Intel
X = Intel
Y = Intel
Z = Mobile Intel
AC = Intel
The Specification Updates for the Pentium
products do not use this convention.
Errata (Sheet 1 of 5)
D-0/ E-0/
No.
0F34h 0F41h 0F49h
S1 X X
S2 X X
S3 X X
S4 X X
S5 X X
S6 X X
S7 X X
S8 X X
S9 X X
S10 X X
S11 X X
S12 X X
S13 X X
S14 X X
S15 X X
S16 X X
S17 X X
S18 X X
S19 X X
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
® ®
Celeron M processor
® ®
Pentium M processor on 90 nm process with 2 MB L2 cache
® ®
Pentium M processor
® ®
Pentium 4 processor with 533 MHz system bus
® ®
Celeron processor in 478-pin package
G-1/ N-0/ R-0/
Plans
0F43h 0F4Ah
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
Fixed
Summary Table of Changes
® ®
processor, Pentium Pro processor, and other Intel
Errata
Transaction is not retired after BINIT#
Invalid opcode 0FFFh requires a ModRM byte
Processor may hang due to speculative page walks to
non-existent system memory
Memory type of the load lock different from its corresponding
store unlock
Machine Check Architecture error reporting and recovery may
not work as expected
Debug mechanisms may not function as expected
Cascading of performance counters does not work correctly
when forced overflow is enabled
EMON event counting of x87 loads may not work as expected
System bus interrupt messages without data and which
receive a hard-failure response may hang the processor
The processor signals page fault exception (#PF) instead of
alignment check exception (#AC) on an unlocked
CMPXCHG8B instruction
FSW may not be completely restored after page fault on
FRSTOR or FLDENV instructions
Processor issues inconsistent transaction size attributes for
locked operation
When the processor is in the system management mode
(SMM), Debug registers may be fully writeable
Shutdown and IERR# may result due to a machine check
exception on a Hyper-Threading Technology enabled
processor
Processor may hang under certain frequencies and 12.5%
STPCLK# duty cycle
System may hang if a fatal cache error causes bus write line
(BWL) transaction to occur to the same cache line address as
an outstanding bus read line (BRL) or bus read-invalidate line
(BRIL)
A write to APIC task priority register (TPR) that lowers priority
may seem to have not occurred
Parity error in the L1 cache may cause the processor to hang
Sequence of locked operations can cause two threads to
receive stale data and cause application hang
13