Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 25

S16 System may hang if a fatal cache error causes bus write line (BWL)
transaction to occur to the same cache line address as an outstanding bus
read line (BRL) or bus read-invalidate line (BRIL)
Problem: A processor internal cache fatal data ECC error may cause the processor to issue a bus write line
(BWL) transaction to the same cache line address as an outstanding bus read line (BRL) or bus
read-invalidate line (BRIL). As it is not typical behavior for a single processor to have a BWL and
a BRL/BRIL concurrently outstanding to the same address, this may represent an unexpected
scenario to system logic within the chipset.
Implication: The processor may not be able to fully execute the machine check handler in response to the fatal
cache error if system logic does not ensure forward progress on the system bus under this scenario.
System logic should ensure completion of the outstanding transactions. Note that during recovery
Workaround:
from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL
transactions is not important. Forward progress is the primary requirement.
For the steppings affected, see the Summary Table of Changes.
Status:
S17 A write to APIC task priority register (TPR) that lowers priority may seem to
have not occurred
Uncacheable stores to the APIC space are handled in a non-synchronous way with respect to the
Problem:
speed at which instructions are retired. If an instruction that masks the interrupt flag (for example
CLI) is executed soon after an uncacheable write to the task priority register (TPR) that lowers the
APIC priority the interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR but higher than the
final TPR to not be serviced until the interrupt flag is finally cleared (for example STI). Interrupts
will remain pended and are not lost
Implication: This condition may allow interrupts to be accepted by the processor but may delay their service
Workaround: This can be avoided by issuing a TPR Read after a TPR Write that lowers the TPR value. This will
force the store to the APIC priority resolution logic before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
S18 Parity error in the L1 cache may cause the processor to hang
If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
Problem:
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S19 Sequence of locked operations can cause two threads to receive stale data
and cause application hang
While going through a sequence of locked operations, it is possible for the two threads to receive
Problem:
stale data. This is a violation of expected memory ordering rules and causes the application to
hang.
When this erratum occurs in an Hyper-Thread Technology enabled system, an application may
Implication:
hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Table of Changes.
Status:
® ®
64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
25