Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 29

store unlock occurs. Correct data is provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8 byte load lock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None at this time.
For the steppings affected, see the Summary Table of Changes.
Status:
S33 Duplicate erratum: see Erratum S5
S34 Execution of IRET and INTn instructions may cause unexpected system
behavior
There is a small window of time, requiring alignment of many internal micro architectural events,
Problem:
during which the speculative execution of the IRET or INTn instructions in protected or IA-32e
mode may result in unexpected software or system behavior.
This erratum may result in unexpected instruction execution, events, interrupts or a system hang
Implication:
when the IRET instruction is executed. The execution of the INTn instruction may cause debug
breakpoints to be missed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
S35 Data breakpoints on the high half of a floating-point line split may not be
captured
When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a
Problem:
data breakpoint register maps to the high line of the floating point load, internal boundary
conditions exist that may prevent the data breakpoint from being captured.
When this erratum occurs, a data breakpoint will not be captured.
Implication:
Workaround: None at this time.
Status: For the steppings affected, see the Summary Table of Changes.
S36 Machine Check Exceptions may not update Last-Exception Record MSRs
(LERs)
The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions
Problem:
occur.
When this erratum occurs, the LER may not contain information relating to the machine check
Implication:
exception. They will contain information relating to the exception prior to the machine check
exception.
None at this time.
Workaround:
Status: For the steppings affected, see the Summary Table of Changes.
S37 MOV CR3 performs incorrect reserved bit checking when in PAE paging
The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented
Problem:
address bits. This checking range should match the address width reported by CPUID instruction
0x8000008. This erratum applies whenever PAE is enabled.
Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.
Implication:
This erratum has not been observed with commercially available software.
None at this time.
Workaround:
Status: For the steppings affected, see the Summary Table of Changes.
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64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update
Errata
29