Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU Processor Specification page 28

Errata
BIOS should initialize the second thread of the processor supporting HT Technology prior to
Workaround:
STPCLK# assertion.
Status: For the steppings affected, see the Summary Table of Changes.
S29 Incorrect duty cycle is chosen when on-demand clock modulation is
enabled in a processor supporting Hyper-Threading Technology
Problem: When a processor supporting HT Technology enables on-demand clock modulation on both logical
processors, the processor is expected to select the lowest duty cycle of the two potentially different
values. When one logical processor enters the AUTOHALT state, the duty cycle implemented
should be unaffected by the halted logical processor. Due to this erratum, the duty cycle is
incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the on-demand clock modulation is
enabled on both logical processors.
None at this time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S30 Memory aliasing of pages as uncacheable memory type and write back
(WB) may hang the system
When a page is being accessed as either UC or write combining (WC) and write back (WB), under
Problem:
certain bus and memory timing conditions, the system may loop in a continual sequence of UC
fetch, implicit write back, and RFO retries
Implication: This erratum has not been observed in any commercially available operating system or application.
The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as
being unsupported in the IA-32 Intel
Section 10.12.4, Programming the PAT. However, if this erratum occurs the system may hang
The pages should not be mapped as either UC or WC and WB at the same time.
Workaround:
For the steppings affected, see the Summary Table of Changes.
Status:
S31 Using STPCLK# and executing code from very slow memory could lead to a
system hang
The system may hang when the following conditions are met:
Problem:
1. Periodic STPCLK# mechanism is enabled via the
2. HT Technology is enabled.
3. One logical processor is waiting for an event (i.e. hardware interrupt).
4. The other logical processor executes code from very slow memory such that every code fetch
is deferred long enough for the STPCLK# to be reasserted.
If this erratum occurs, the processor will go into and out of the sleep state without making forward
Implication:
progress, since the logical processor will not be able to service any pending event. This erratum has
not been observed in any commercial platform running commercial software.
None at this time.
Workaround:
Status: For the steppings affected, see the Summary Table of Changes.
S32 Processor provides a 4-byte store unlock after an 8-byte load lock
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
28
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Architecture Software Developer's Manual, Volume 3,
chipset.
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64-bit Intel Xeon Processor with 800 MHz System Bus
(1 MB and 2 MB L2 Cache Versions) Specification Update