Ppga Package Signal Listing By Pin Number - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
Pin
No.
N37
P2
P4
P6
P32
P34
P36
Q1
Q3
Q5
Q33
Q35
Q37
R2
R4
R6
R32
R34
R36
S1
S3
S5
S33
S35
S37
T2
T4
T6
T32
T34
T36
U1
U3
86
by Pin Number
Pin Name Signal Buffer Type
Reserved Reserved for Future Use
V Power/Other
CC CORE
D18# AGTL+ I/O
D9# AGTL+ I/O
V Power/Other
SS
V Power/Other
CC CORE
V Power/Other
SS
D12# AGTL+ I/O
D10# AGTL+ I/O
V Power/Other
SS
Reserved Reserved for Future Use
Reserved Reserved for Future Use
Reserved Reserved for Future Use
Reserved Reserved for Future Use
D17# AGTL+ I/O
V 3 Power/Other
REF
V Power/Other
CC CORE
V Power/Other
SS
V Power/Other
CC CORE
D8# AGTL+ I/O
D5# AGTL+ I/O
V Power/Other
CC CORE
Reserved Reserved for Future Use
Reserved Reserved for Future Use
Reserved Reserved for Future Use
V Power/Other
CC CORE
D1# AGTL+ I/O
D6# AGTL+ I/O
V Power/Other
SS
V Power/Other
CC CORE
V Power/Other
SS
D4# AGTL+ I/O
D15# AGTL+ I/O
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name
U5 V Power/Other
SS
U33 PLL2 Power/Other
U35 Reserved Reserved for Future Use
U37 Reserved Reserved for Future Use
V2 V Power/Other
SS
V4 Reserved Reserved for Future Use
V6 V 4 Power/Other
REF
V32 V Power/Other
CC CORE
V34 V Power/Other
SS
V36 V Power/Other
CC CORE
W1 D0# AGTL+ I/O
W3 Reserved Reserved for Future Use
W5 V Power/Other
CC CORE
W33 PLL1 Power/Other
W35 Reserved Reserved for Future Use
W37 BCLK System Bus Clock Input
X2 Reserved Reserved for Future Use
X4 RESET# AGTL+ Input
X6 Reserved Reserved for Future Use
X32 V Power/Other
SS
X34 V Power/Other
CC CORE
X36 V Power/Other
SS
Y1 Reserved Reserved for Future Use
Y3 A26# AGTL+ I/O
Y5 V Power/Other
SS
Y33 V Power/Other
SS
Y35 V Power/Other
CC CORE
Y37 V Power/Other
SS
Z2 V Power/Other
SS
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 V Power/Other
CC CORE
Z34 V Power/Other
SS
Z36 V Power/Other
CC 2.5
Signal Buffer Type
Datasheet