Electrical Specifications; System Bus And Vref; Clock Control And Low Power States - Intel CELERON 1.10 GHZ Datasheet

2.0

Electrical Specifications

2.1 System Bus and V
Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL)
signaling technology. The Intel Celeron processor system bus specification is similar to the GTL
specification, but has been enhanced to provide larger noise margins and reduced ringing. The
improvements are accomplished by increasing the termination voltage level and controlling the
edge rates. Because this specification is different from the standard GTL specification, it is referred
to as Assisted Gunning Transceiver Logic (AGTL+) in this document.
The Celeron processor varies from the Pentium Pro processor in its output buffer implementation.
The buffers that drive the system bus signals on the Celeron processor are actively driven to
V
CC CORE
reduces overshoot. These signals should still be considered open-drain and require termination to a
supply that provides the logic-high signal level.
The AGTL+ inputs use differential receivers which require a reference signal (V
by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the
processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370
socket). Local V
AGTL+ system bus.
Termination is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor may contain termination resistors (S.E.P. Package, FC-PGA
Package, and FC-PGA2 Package) that provide termination for one end of the Intel Celeron
processor system bus. Otherwise, this termination must exist on the motherboard.
Solutions exist for single-ended termination as well, though this implementation changes system
design and eliminate backwards compatibility for Celeron processors in the PPGA package.
Single-ended termination designs must still provide an AGTL+ termination resistor on the
motherboard for the RESET# signal.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on motherboard flight time as opposed to capacitive deratings. Analog signal
simulation of the Intel Celeron processor system bus, including trace lengths, is highly
recommended when designing a system. See the Pentium
and the Pentium
2.2

Clock Control and Low Power States

Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce
power consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See
states.
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (hex), bit 26
must be set to a '1' (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Pentium
(Order Number 243502).
Datasheet
REF
for one clock cycle during the low-to-high transition. This improves rise times and
copies should be generated on the motherboard for all other devices on the
REF
®
II Processor I/O Buffer Models, Quad Format (Electronic Form) for details.
Figure 1 for a visual representation of the Intel Celeron processor low power
® ®
Intel Celeron Processor up to 1.10 GHz
®
II Processor AGTL+ Layout Guidelines
®
II Processor Developer's Manual
). V is used
REF REF
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