Signal Summaries; Output Signals - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
Signal
V
CORE DET
(PGA packages
only)
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
V [7:0]
REF
(PGA packages
only)
7.1

Signal Summaries

Table 60
Table 60. Output Signals
Name
CPUPRES# (PGA
packages only)
FERR#
IERR#
PRDY#
SLOTOCC#
(S.E.P.P. only)
THERMDN
THERMTRIP#
V
CORE DET
(PGA packages only)
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages)
126
Type
The V
CORE DET
O
®
Celeron FC-PGA/FC-PGA2 processor with a 1.5V core voltage.
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS
O voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
I
signal is a logic high or logic low.
For the FC-PGA/FC-PGA2 packages, V
through Table 63 list attributes of the Celeron processor output, input, and I/O signals.
Active Level
Low
Low
Low
Low
Low
TDO High
N/A
Low
High
High
Description
signal will float for 2.0 V core processors and will be grounded for the
on the processor. The combination of opens and shorts defines the
REF
Clock
Asynch
Asynch
Asynch
BCLK
Asynch
TCK
Asynch
Asynch
Asynch
Asynch
Table 2
is typically 2/3 of V
TT
Signal Group
Power/Other
CMOS Output
CMOS Output
AGTL+ Output
Power/Other
TAP Output
Power/Other
CMOS Output
Power/Other
Power/Other
Datasheet
for