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Intel P4000 - DATASHEET REV 001 Datasheet

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Intel® Celeron® Mobile Processor
P4000 and U3000 Series
Datasheet
Revision 001
October 2010
Document Number: 324471-001

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Summary of Contents for Intel P4000 - DATASHEET REV 001

  • Page 1 Intel® Celeron® Mobile Processor P4000 and U3000 Series Datasheet Revision 001 October 2010 Document Number: 324471-001...
  • Page 2 Intel, Intel SpeedStep, Celeron, Intel vPro and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2010, Intel Corporation. All rights reserved.

  • Page 3: Table Of Contents

    Platform Environment Control Interface (PECI) ........... 14 1.3.5 Intel® HD Graphics Controller..............14 1.3.6 Embedded DisplayPort* (eDP*) ..............15 1.3.7 Intel® Flexible Display Interface (Intel® FDI) ..........15 Power Management Support ................15 1.4.1 Processor Core ..................15 1.4.2 System ....................15 1.4.3...
  • Page 4 Thermal Power Management ................52 Thermal Management ....................53 Thermal Design Power and Junction Temperature...........53 5.1.1 Intel Graphics Dynamic Frequency ............53 5.1.2 Intel Graphics Dynamic Frequency Thermal Design Considerations and Specifications ..................54 5.1.3 Idle Power Specifications .................56 5.1.4 Intelligent Power Sharing Control Overview ..........57 5.1.5...
  • Page 5 Processor Pin and Signal Information ..............105 Processor Pin Assignments................105 Package Mechanical Information................ 179 Figures Figure 1-1 Intel® Celeron™ P4000 and U3000 mobile processor series on the Calpella Platform ....................10 Figure 2-2 Intel Flex Memory Technology Operation ........... 22 Figure 2-3 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes .
  • Page 6 Coordination of Core Power States at the Package Level.......46 Table 4-16 Targeted Memory State Conditions............50 Table 5-17 Intel Celeron P4000 mobile processor series Dual-Core SV Thermal Power Specifications ..................56 Table 5-18 18 W Ultra Low Voltage (ULV) Processor Idle Power ........56 Table 5-19 35 W Standard Voltage (SV) Processor Idle Power........57...
  • Page 7 Table 7-40 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications Table 7-41 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications..98 Table 7-42 Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications..................99 Table 7-43 DDR3 Signal Group DC Specifications ............

  • Page 8: Revision History

    Revision History Revision Description Revision Date Number Initial release October 2010 § Datasheet...

  • Page 9: Features Summary

    Calpella platform and is offered in rPGA988A and BGA1288 package respectively. Included in this family of processors is Intel® HD graphics and memory controller die on the same package as the processor core die. This two-chip solution of a processor core die with an integrated graphics and memory controller die is known as a multi-chip package (MCP) processor.

  • Page 10: Figure 1-1 Intel® Celeron™ P4000 And U3000 Mobile Processor Series On The Calpella

    Features Summary Figure 1-1. Intel® Celeron® P4000 and U3000 mobile processor series on the Calpella Platform Dual Core Processor Discrete Graphics (PEG) PCI Express* x16 800/1066 MT/s Processor 2 Channels Embedded 1 SO-DIMM / Channel GPU, Memory DisplayPort* (eDP) Controller...

  • Page 11: Processor Feature Details

    Intel® Virtualization Technology (Intel® VT-x) • Intel® 64 architecture • Execute Disable Bit Note: Please refer to the Intel® Celeron® P4000 and U3000 mobile processor series Specification Update for feature support details Interfaces 1.3.1 System Memory Support • One or two channels of DDR3 memory with a maximum of one SO-DIMM per channel •...

  • Page 12: Pci Express

    Command launch modes of 1n/2n • Partial Writes to memory using Data Mask (DM) signals • On-Die Termination (ODT) • Intel® Fast Memory Access (Intel® FMA): — Just-in-Time Command Scheduling — Command Overlap — Out-of-Order Scheduling 1.3.2 PCI Express* •...

  • Page 13: Direct Media Interface (Dmi)

    Features Summary non-zero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped. • Re-issues configuration cycles that have been previously completed with the Configuration Retry status. • PCI Express reference clock is 100-MHz differential clock buffered out of system clock generator.

  • Page 14: Platform Environment Control Interface (Peci)

    — Sharpness Enhancement — De-noise Filter — High Quality Scaling — Film Mode Detection (3:2 pull-down) and Correction — Intel® TV Wizard • 12 EUs • Dedicated analog and digital display ports are supported through the Intel 5 Series Chipset PCH Datasheet...

  • Page 15: Embedded Displayport* (Edp*)

    — FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization) • One Interrupt signal used for various interrupts from the PCH: — FDI_INT signal shared by both Intel FDI Links • PCH supports end-to-end lane reversal across both links. Power Management Support 1.4.1...

  • Page 16: Memory Controller

    Fan speed control with DTS Package • The Intel® Celeron® P4000 and U3000 mobile processor series is available is available on: — A 37.5 x 37.5 mm rPGA package (rPGA988A) (Standard Voltage only) — A 34 x 28 mm BGA package (BGA1288) (Ultra Low voltage only)

  • Page 17: Terminology

    Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. Nehalem Intel’s 45-nm processor design, follow-on to the 45-nm Penryn design. Datasheet...
  • Page 18 I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. The PCH may also be referred to using the name (Mobile) Intel® 5 Series Chipset PECI Platform Environment Control Interface.

  • Page 19: Related Documents

    PCI Express Base Specification 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.org DisplayPort Specification http://www.vesa.org Intel® 64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/ products/processor/ manuals/index.htm Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z...

  • Page 20: Interfaces

    Interfaces Interfaces This chapter describes the interfaces supported by the processor. System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels each accessing one SO-DIMM. It supports a maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up to two device ranks per-channel.

  • Page 21: System Memory Timing Support

    Interfaces Table 2-1. Supported SO-DIMM Module Configurations # of # of Row/ # of DRAM # of DIMM DRAM Physical Banks Page Card Device DRAM Capacity Organization Device Address Inside Size Version Technology Devices Ranks Bits DRAM 4 GB 2 Gb 256 M x 8 15/10 2 GB...

  • Page 22: Figure 2-2 Intel Flex Memory Technology Operation

    2.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The...

  • Page 23: Rules For Populating Memory Slots

    This mode is used when Intel Flex Memory Technology is disabled and both Channel A and Channel B SO-DIMM connectors are populated in any order with the total amount of memory in each channel being different.

  • Page 24: Fma)

    ® (Intel FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.

  • Page 25: Pci Express Interface

    Interfaces PCI Express Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device or two external x8 PCI Express Graphics Devices.

  • Page 26: Figure 2-5 Packet Flow Through The Layers

    Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-5. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer.

  • Page 27: Pci Express Configuration Mechanism

    Interfaces 2.2.2 PCI Express Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-6. PCI Express Related Register Structures in the Processor PCI-PCI Bridge Compatible PEG0 representing Express Host Bridge root PCI Device Device Express port (Device 0)

  • Page 28: Dmi

    Interfaces 2.2.3.1 PCI Express Bifurcated Mode When bifurcated, the signals which had previously been assigned to Lanes 15:8 of the single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary Port. This assignment applies whether the lane numbering is reversed or not. PCI Express Port 0 is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6.

  • Page 29: Intel® Hd Graphics Controller

    Intel FDI. The integrated graphics has a 3D/2D Instruction Processing unit to control the 3D and 2D engines respectively. The integrated graphics controller’s 3D and 2D engines are fed with data through the IMC.
  • Page 30 Interfaces • Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing. 2.4.1.2 3D Pipeline 2.4.1.2.1 Vertex Fetch (VF) Stage The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*. 2.4.1.2.2 Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function.
  • Page 31 Interfaces 2.4.1.3 Video Engine The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware. 2.4.1.4 2D Engine The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of 2D instructions. To take advantage of the 3D during engine’s functionality, some BLT functions make use of the 3D renderer.

  • Page 32: Integrated Graphics Display Pipes

    The integrated graphics controller display pipe can be broken down into three components: • Display Planes • Display Pipes • Embedded DisplayPort and Intel FDI Figure 2-8. Processor Display Block Diagram Plane A Sprite A Pipe A Cursor A Alpha...

  • Page 33: Table 2-3 Edp/Peg Ball Mapping

    The display pipes A and B operate independently of each other at the rate of 1 pixel per clock. They can attach to any of the display ports. Each pipe sends display data to the PCH over the Intel Flexible Display Interface (Intel FDI). 2.4.2.3...

  • Page 34: Intel Flexible Display Interface

    2.4.3 Intel Flexible Display Interface The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display traffic from the integrated graphics controller to the PCH display I/O’s. Intel FDI supports two independent channels; one for pipe A and one for pipe B.

  • Page 35: Interface Clocking

    Read averaged Digital Thermal Sensor (DTS) values for fan speed control. Interface Clocking 2.6.1 Internal Clocking Requirements Table 2-4. Processor Reference Clocks Reference Input Clocks Input Frequency Associated PLL BCLK/BCLK# 133 MHz Processor/Memory/Graphics PEG_CLK/PEG_CLK# 100 MHz PCI Express*/DMI/Intel® FDI DPLL_REF_SSCLK/DPLL_REF_SSCLK# 120 MHz Embedded DisplayPort* (eDP) § Datasheet...

  • Page 36: Technologies

    OSs and applications without any special steps. • Enhanced—Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable—Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.

  • Page 37: Intel Graphics Dynamic Frequency

    Intel Graphics Dynamic Frequency Graphics render frequency are selected by the Intel graphics driver dynamically based on graphics workload demand as permitted by Intel Turbo Boost Technology Driver. The processor core die and the integrated graphics and memory controller core die have an individual TDP limit.

  • Page 38: Power Management

    Power Management Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • Integrated Memory Controller (IMC) • PCI Express • Direct Media Interface (DMI) • Integrated Graphics Controller ACPI States Supported The ACPI states supported by the processor are described in this section.

  • Page 39: Integrated Memory Controller States

    Power Management 4.1.3 Integrated Memory Controller States Table 4-7. Integrated Memory Controller States State Description Power up CKE asserted. Active mode. Pre-charge Power down CKE deasserted (not self-refresh) with all banks closed. Active Power down CKE deasserted (not self-refresh) with minimum one bank active. Self-Refresh CKE deasserted using device self-refresh.

  • Page 40: Interface State Combinations

    Processor Core Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle.

  • Page 41: Enhanced Intel Speedstep® Technology

    Power Management 4.2.1 Enhanced Intel SpeedStep® Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.

  • Page 42: Figure 4-9 Idle Power Management Breakdown Of The Processor Cores

    Power Management Figure 4-9. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 0 Core 0 State Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in below figure. Figure 4-10.Thread and Core C-State Entry and Exit MWAIT(C1), HLT MWAIT(C6),...

  • Page 43: Requesting Low-Power Idle States

    Power Management Table 4-13.Coordination of Thread Power States at the Core Level Thread 1 Processor Core C-State NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

  • Page 44: Core C-States

    MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.

  • Page 45: Package C-States

    Power Management 4.2.4.4 Core C6 State Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.

  • Page 46: Table 4-15 Coordination Of Core Power States At The Package Level

    Power Management The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: • If a core break event is received, the target core is activated and the break event message is forwarded to the target core.

  • Page 47: Figure 4-11 Package C-State Entry And Exit

    Power Management Figure 4-11.Package C-State Entry and Exit 4.2.5.1 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state.

  • Page 48: Imc Power Management

    Power Management No notification to the system occurs upon entry to C1/C1E. 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform.

  • Page 49: Disabling Unused System Memory Outputs

    Power Management 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as SO-DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: •...

  • Page 50: Pcie Power Management

    Power Management Table 4-16.Targeted Memory State Conditions Mode Memory State with Internal Graphics Memory State with External Graphics C0, C1, C1E Dynamic memory rank power down based on Dynamic memory rank power down based on idle conditions. idle conditions. C3, C6 If the internal graphics engine is idle and there If there are no memory requests, then enter are no pending display requests when in single...

  • Page 51: Dmi Power Management

    As a result, the display backlight power can be reduced by up to 25% depending on Intel DPST settings and system use. Intel DPST 5.0 provides enhanced image quality over the previous version of Intel DPST.

  • Page 52: Thermal Power Management

    Power Management Thermal Power Management • Section 5, “Thermal Management” on page 53 for all graphics thermal power management-related features. § Datasheet...

  • Page 53: Thermal Management

    MCP thermal power limit. On this processor, Intel Graphics Dynamic Frequency is implemented via a combination of Intel silicon capabilities, graphics driver and the Intel Turbo Boost Technology driver. If Intel provides Intel Graphics Dynamic Frequency support for the target operating...

  • Page 54: Intel Graphics Dynamic Frequency Thermal Design Considerations And Specifications

    Thermal Management system that is shipped with the customer’s platform and Intel Graphics Dynamic Frequency is enabled, the Intel Turbo Boost Technology driver and graphics driver must be installed and operating to keep the product operating within specification limits. Caution: The TURBO_POWER_CURRENT_LIMIT MSR is exclusively reserved for Intel Turbo Technology Driver use.
  • Page 55 While running intensive graphical and computational workloads simultaneously the concurrent package power may exceed specified limits in exceptional occasions. Nevertheless, the individual component powers are not to exceed the component TDPs specified. Intel Celeron Mobile Processor U3000 Series Dual-Core ULV Thermal Power Specifications Power Sharing Design 1,2,6,7...

  • Page 56: Idle Power Specifications

    Thermal Management Table 5-17.Intel Celeron Mobile Processor P4000 Series Dual-Core SV Thermal Power Specifications Power Sharing Design 1,2,6,7 4,5,10,12 Frequency j,max Points Proc: Proc: 12.5 1.86 up to Int. Gfx: 6 Gfx:20 12.5 32.5 933 MHz Proc: Proc: 12.5 2.00 up to Int.

  • Page 57: Intelligent Power Sharing Control Overview

    Intel Turbo Boost Technology performance dynamically, to stay within the limit. Note: The processor PECI pin must be connected to the PCH PECI pin in order for Intel Turbo Boost Technology to properly function. Datasheet...

  • Page 58: Component Power Measurement/Estimation Error

    GFX driver using PMON. Any error in power estimation or measurement may limit or completely eliminate the performance benefit of Intel Turbo Boost Technology. When a power limit is reached, Power sharing control will adaptively remove Intel Turbo Boost Technology states to remain with the MCP thermal power limit.
  • Page 59 The Adaptive Thermal Monitor dynamically selects the appropriate method. BIOS is not required to select a specific method as with previous-generation processors supporting Intel® Thermal Monitor 1 (TM1) or Intel® Thermal Monitor 2 (TM2). The temperature at which the Adaptive Thermal Monitor activates the Thermal Control Circuit is not user configurable but is software visible in the IA32_TEMPERATURE_TARGET (0x1A2) MSR, Bits 23:16.

  • Page 60: Figure 5-12 Frequency And Voltage Ordering

    It will be necessary to transition through multiple VID steps to reach the target operating voltage. • Each step is 12.5 mV for Intel MVP-6.5 compliant VRs. • The processor continues to execute instructions. However, the processor will halt instruction execution for frequency transitions.

  • Page 61: Digital Thermal Sensor

    When temperature is retrieved via PECI, it is the average temperature of each execution core’s DTS over a programmable window (default window of 256 ms.) Intel recommends using the PECI output reading for fan speed or other platform thermal control.
  • Page 62 Changes to the temperature can be detected via two programmable thresholds located in the processor thermal MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
  • Page 63 Thermal Management 5.2.1.3.2 Voltage Regulator Protection PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption.
  • Page 64 MSR register and also generates a thermal interrupt if enabled. The assertion of critical temperature bit indicates that processor can no longer be assumed to be working reliably.For more details on the interrupt mechanism, refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals.

  • Page 65: Integrated Graphics And Memory Controller Thermal Features

    Thermal Management 5.2.2 Integrated Graphics and Memory Controller Thermal Features The integrated graphics and memory controller provides the following features for monitoring the integrated graphics and memory controller temperature and triggering thermal management: • One internal digital thermal sensor • Hooks for an external thermal sensor mechanism which can either be TS-on-DIMM or TS-on-Board The integrated graphics and memory controller has implemented several silicon level...
  • Page 66 Thermal Management 5.2.2.1.3 Catastrophic Trip Point This trip point is set at the temperature at which the integrated graphics and memory controller must be shut down immediately without any software support. This trip point may be programmed to generate an interrupt, enable throttling, or immediately shut down the system (via Halt or via THERMTRIP# assertion).
  • Page 67 The TDP Controller can also be used as a bandwidth limiter using programmable memory read/write bandwidth thresholds. Intel sets the default thresholds that will not restrict bandwidth and performance for most applications but these thresholds can be modified to reduce MCH power regardless of DTS temperature.

  • Page 68: Platform Environment Control Interface (Peci)

    Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control.
  • Page 69 Thermal Management 5.2.3.2 Processor Thermal Data Sample Rate and Filtering The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. To reduce the sample rate requirements on PECI and improve thermal data stability vs.

  • Page 70: Signal Description

    Express 2.0 Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-V tolerant. Refer to the PCIe specification. Intel Flexible Display interface signals. These signals are compatible with PCI Express 2.0 Signaling Environment AC Specifications, but are DC coupled.

  • Page 71: System Memory Interface

    Signal Description System Memory Interface Table 6-21.Memory Channel A (Sheet 1 of 2) Direction/Buffer Signal Name Description Type SA_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. DDR3 SA_WE# Write Enable Control Signal: Used with SA_RAS# and SA_CAS# (along with DDR3 SA_CS#) to define the SDRAM Commands.

  • Page 72: Table 6-22 Memory Channel B

    Signal Description Table 6-21.Memory Channel A (Sheet 2 of 2) Direction/Buffer Signal Name Description Type SA_CKE[1:0] Clock Enable: (1 per rank) Used to: - Initialize the SDRAMs during power-up DDR3 - Power-down SDRAM ranks - Place all SDRAM ranks into and out of self- refresh during STR SA_CS#[1:0] Chip Select: (1 per rank) Used to select...

  • Page 73: Memory Reference And Compensation

    Signal Description Table 6-22.Memory Channel B (Sheet 2 of 2) Direction/ Signal Name Description Buffer Type SB_MA[15:0] Memory Address: These signals are used to provide the multiplexed row and column DDR3 address to the SDRAM. SB_CK[1:0] SDRAM Differential Clock: Channel B SDRAM Differential clock signal pair.

  • Page 74: Reset And Miscellaneous Signals

    Signal Description Reset and Miscellaneous Signals Table 6-24.Reset and Miscellaneous Signals (Sheet 1 of 2) Direction/Buffer Signal Name Description Type SM_DRAMRST# DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One for all DDR3 channels or SO-DIMMs. PM_EXT_TS#[0] External Thermal Sensor Input: If the system temperature reaches a dangerously PM_EXT_TS#[1] CMOS...

  • Page 75: Pci Express Graphics Interface Signals

    RESERVED. All signals that are RSVD and No Connect RSVD_NCTF must be left unconnected on the RSVD_TP Test Point board. However, Intel recommends that all RSVD_NCTF Non-Critical to RSVD_TP signals have via test points. Function PCI Express Graphics Interface Signals Table 6-25.PCI Express Graphics Interface Signals...

  • Page 76: Embedded Displayport (Edp)

    Embedded DisplayPort Resistance Compensation: Multiplexed with PEG_RCOMPO eDP_RBIAS Embedded DisplayPort Resistor Bias Control: Multiplexed with PEG_RBIAS Intel Flexible Display Interface Signals Table 6-26.Intel® Flexible Display Interface (Sheet 1 of 2) Direction/Buffer Signal Name Description Type FDI_TX[3:0] Intel® Flexible Display Interface...

  • Page 77: Dmi

    Signal Description Table 6-26.Intel® Flexible Display Interface (Sheet 2 of 2) Direction/Buffer Signal Name Description Type FDI_TX[7:4] Intel® Flexible Display Interface Transmit Differential Pair - Pipe B FDI_TX#[7:4] FDI_FSYNC[1] Intel® Flexible Display Interface Frame Sync - Pipe B CMOS FDI_LSYNC[1] Intel®...

  • Page 78: Tap Signals

    Signal Description TAP Signals Table 6-29.TAP Signals Direction/Buffer Signal Name Description Type TCK (Test Clock): Provides the clock input for the processor Test Bus (also known as CMOS the Test Access Port). TDI (Test Data In): Transfers serial test data into the processor. TDI provides the CMOS serial input needed for JTAG specification support.

  • Page 79: Error And Thermal Protection

    Signal Description 6.10 Error and Thermal Protection Table 6-30.Error and Thermal Protection Direction/Buffer Signal Name Description Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

  • Page 80: Power Sequencing

    Signal Description 6.11 Power Sequencing Table 6-31.Power Sequencing Direction/Buffer Signal Name Description Type VCCPWRGOOD_0 VCCPWRGOOD_0 and VCCPWRGOOD_1 (Power Good) Processor Input: The VCCPWRGOOD_1 Asynchronous CMOS processor requires these signals to be a clean indication that: -VCC, VCCPLL, and VTT supplies are stable and within their specifications -BCLK is stable and has been running for a minimum number of cycles.

  • Page 81: Processor Power Signals

    DDR3 power rail (1.5 V) VCCPLL Power rail for filters and PLLs (1.8 V) ISENSE Current Sense from an Intel® MVP6.5 Compliant Regulator to the processor core. PROC_DPRSLPVR Processor output signal to Intel MVP-6.5 controller to indicate that the processor is in CMOS the package C6 state.
  • Page 82 The VTT_SELECT signal is used to select the correct VTT voltage level for the processor. CMOS VCC_SENSE Voltage Feedback Signals to an Intel MVP-6.5 Compliant VR: Use VCC_SENSE to sense VSS_SENSE voltage and VSS_SENSE to sense ground near the silicon with little noise.

  • Page 83: Ground And Nctf

    Direction/Buffer Signal Name Description Type GFX_DPRSLPVR GPU output signal to Intel MVP6.5 compliant VR. When asserted this signal indicates that CMOS the GPU is in render suspend mode. This signal is also used to control render suspend state exit slew rate.
  • Page 84 Signal Description Table 6-34.Processor Internal Pull Up/Pull Down Signal Name Pull Up/Pull Down Rail Value TDI_M Pull Up 44 - 55 kΩ PREQ# Pull Up 44 - 55 kΩ CFG[17:0] Pull Up 5 - 14 kΩ § Datasheet...

  • Page 85: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins The processor has V and V (ground) inputs for on-chip DDQ, CCPLL, power distribution. All power pins must be connected to their respective processor power planes, while all V pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.

  • Page 86: Pll Power Supply

    Electrical Specifications 7.3.1 PLL Power Supply An on-die PLL filter solution is implemented on the processor. Refer to Table 7-35 DC specifications Voltage Identification (VID) The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of the processor power supply voltages. VID pins for the processor are CMOS outputs driven by the processor VID circuitry.
  • Page 87 Electrical Specifications Table 7-35.Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000...
  • Page 88 Electrical Specifications Table 7-35.Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250...
  • Page 89 Electrical Specifications Table 7-35.Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000...

  • Page 90: Reserved Or Unused Signals

    Electrical Specifications Table 7-36.Market Segment Selection Truth Table for MSID[2:0] MSID[2] MSID[1] MSID[0] Description Notes Reserved Reserved Reserved Reserved Standard Voltage (SV) 35-W Supported Reserved Reserved Reserved NOTES: MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. MSID is used on rPGA988A platforms only.

  • Page 91: Signal Groups

    Electrical Specifications Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-37. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On-Die Termination (ODT) resistors.
  • Page 92 Electrical Specifications Table 7-37.Signal Groups (Sheet 2 of 3) Alpha Signal Group Type Signals Group Control Sideband Single Ended (ja) Asynchronous CCPWRGOOD_0 CCPWRGOOD_1 TTPWRGOOD CMOS Input Single Ended (jb) Asynchronous SM_DRAMPWROK CMOS Input Single Ended Asynchronous RESET_OBS# CMOS Output Single Ended Asynchronous GTL PRDY#, THERMTRIP# Output...

  • Page 93: Test Access Port (Tap) Connection

    Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.

  • Page 94: Absolute Maximum And Minimum Ratings

    Electrical Specifications Absolute Maximum and Minimum Ratings Table 7-38 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on...

  • Page 95: Dc Specifications

    JESD22-A103 (high temp) standards when applicable for volatile memory. Intel® branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40°C to 70°C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28°C.) Post board attach storage temperature limits...

  • Page 96: Voltage And Current Specifications

    CC_MAX Processor core VR to be designed to electrically support this current Processor core VR to be designed to thermally support this current indefinitely. This specification assumes that Intel Turbo Boost Technology with Intelligent Power Sharing is enabled. Datasheet...

  • Page 97: Figure 7-13.Active V

    Electrical Specifications Figure 7-13.Active V and I Loadline (PSI# Asserted) [ V ] S l o p e = S L O P E V C C _ S E N S E , V S S _ S E N S E p i n s . D i f f e r e n t i a l R e m o t e S e n s e r e q u i r e d .

  • Page 98: Table 7-41 Processor Uncore I/O Buffer Supply Dc Voltage And Current Specifications

    Electrical Specifications Table 7-41.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Unit Note Voltage for the memory controller and shared cache defined at the 0.9975 1.05 1.1025 motherboard Vtt pinfield via Voltage for the memory controller and shared cache defined across 0.9765 1.05...

  • Page 99: Figure 7-15 Vaxg/Iaxg Static And Ripple Voltage Regulation

    Minimum values assume Graphics Render C-state (RC6) is enabled. is a VID-Based rail driven by an Intel MVP6.5 compliant voltage regulator. This specification assumes Intel Turbo Boost Technology with Intelligent Power Sharing is enabled. Figure 7-15.V Static and Ripple Voltage Regulation...

  • Page 100: Table 7-43 Ddr3 Signal Group Dc Specifications

    Electrical Specifications Table 7-43.DDR3 Signal Group DC Specifications Alpha Symbol Parameter Units Notes Group Input Low Voltage (e,f) 0.43*V Input High Voltage (e,f) 0.57*V Output Low Voltage (c,d,e,f) / 2)* (R VTT_TERM Output High Voltage (c,d,e,f) - ((V 2)* (R VTT_TERM DDR3 Clock Buffer On Ω...

  • Page 101: Table 7-44 Control Sideband And Tap Signal Group Dc Specifications

    Electrical Specifications Table 7-44.Control Sideband and TAP Signal Group DC Specifications Symbol Alpha Group Parameter Units Notes (m),(n),(p),(s) Input Low Voltage 0.64 (m),(n),(p),(s) Input High Voltage 0.76 2,3,5 Input Low Voltage 0.25 Input High Voltage 0.80 2,3,5 (ga) Input Low Voltage (ga) Input High Voltage 0.75...

  • Page 102: Table 7-45 Pci Express Dc Specifications

    Electrical Specifications Table 7-45.PCI Express DC Specifications Alpha Symbol Parameter Units Notes Group (ad) Differential Peak-to-Peak Tx Voltage TX-DIFF-p-p Swing (ad) Tx AC Peak Common Mode Output 1,2,6 TX_CM-AC-p Voltage (Gen 1 Only) (ad) DC Differential Tx Impedance 1,10 Ω TX-DIFF-DC (Gen 1 Only) (ac)

  • Page 103: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external Adaptive Thermal Monitor devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 104: Input Device Hysteresis

    Electrical Specifications Table 7-47.PECI DC Electrical Limits Symbol Definition and Conditions Units Notes Input Voltage Range -0.150 Hysteresis 0.1 * V hysteresis Negative-edge Threshold Voltage 0.275 * V 0.500 * V Positive-edge Threshold Voltage 0.550 * V 0.725 * V High-Level Output Source -6.0 source...

  • Page 105: Processor Pin And Signal Information

    Processor Pin and Signal Information Processor Pin and Signal Information Processor Pin Assignments • Provides a listing of all processor pins ordered alphabetically by pin name for the rPGA988A and BGA1288 package respectively. • Table 8-48 Table 8-51 provides a listing of all processor pins ordered alphabetically by pin number for the rPGA988A and BGA1288 package respectively •...

  • Page 106: Figure 8-17 Socket-G (Rpga988A) Pinmap (Top View, Upper-Left Quadrant)

    Processor Pin and Signal Information Figure 8-17.Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant) SB _CK# [ V TT0 SB _CK[ 0] V DDQ SA_M A[ 15 SA _M A [ 6 V SS SB_CK[ 1] V TT0 RSV D V SS SA _B S[ 2] V TT0 RSV D...

  • Page 107: Figure 8-18 Socket-G (Rpga988A) Pinmap (Top View, Upper-Right Quadrant)

    Processor Pin and Signal Information Figure 8-18.Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant) VSSAXG_SE SA_DQ[59 SA_DQS# COM P3 VAXG VAXG VAXG VAXG PECI VAXG_SEN SA_DQ[6 SA_DQS[ VAXG VAXG VAXG VAXG PM _EXT_ SA_DQ[6 GFX_VID[3] GFX_VID[1] VAXG VAXG VAXG VAXG TS# [1] PM _EXT_ VCCPWR SA_DM [7...

  • Page 108: Figure 8-19 Socket-G (Rpga988A) Pinmap (Top View, Lower-Left Quadrant)

    Processor Pin and Signal Information Figure 8-19.Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant) V CC V CC VC C V CC VC C V C C VS S VS S V SS VS S V S S V CC V CC VC C V CC VC C...

  • Page 109: Figure 8-20 Socket-G (Rpga988A) Pinmap (Top View, Lower-Right Quadrant)

    Processor Pin and Signal Information Figure 8-20.Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant) SA _B S[ SA_MA[ SB_MA[ SA_MA[ V TT0 RSVD VDDQ SB_MA[ SB_MA[ SA_MA[ SA _MA[ SA_MA [ V TT0 RSVD VDDQ VDDQ RS VD_T RSVD_T SB _B S[ SB_MA[ SB_MA[ SB_MA[...

  • Page 110: Table 8-48 Rpga988A Processor Pin List By Pin Number

    Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin List by Pin Number Table 8-48.rPGA988A Processor Pin Buffer List by Pin Number Pin Name Dir. Number Type Buffer Pin Name Dir. RSVD_NCTF Number Type VSS_NCTF RSVD_TP RSVD_NCTF RSVD_TP SB_DQ[6] DDR3 SA_MA[3] DDR3 SB_DQ[1]...
  • Page 111 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type AB30 AD26 AB31 AD27 AB32 AD28 AB33 AD29 AB34 AD30...
  • Page 112 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_MA[13] DDR3 SB_DQ[39] DDR3 SA_ODT[1] DDR3 SA_DQ[32] DDR3 AF10 VTT0...
  • Page 113 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQ[38] DDR3 SB_DQ[44] DDR3 SA_DQ[34] DDR3 SA_DQ[39] DDR3 SA_DQ[35] DDR3...
  • Page 114 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQS[5] DDR3 SB_DQ[42] DDR3 SA_DM[5] DDR3 SA_DQ[45] DDR3 SA_DQ[47] DDR3...
  • Page 115 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQ[49] DDR3 SB_DQ[48] DDR3 SB_DQ[51] DDR3 SB_DQ[56] DDR3 SA_DQ[48] DDR3...
  • Page 116 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type RSVD_NCTF RSVD_TP RSVD_NCTF RSVD_NCTF SB_DQ[50] DDR3 SB_DM[6] DDR3 SB_DQ[54] DDR3...
  • Page 117 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type VSS_NCTF SB_DQ[12] DDR3 VSS_NCTF SB_DQ[2] DDR3 SB_DQ[3] DDR3 SB_DQ[7] DDR3...
  • Page 118 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQ[4] DDR3 SB_DM[0] DDR3 SB_DQS#[0] DDR3 SA_DQ[10] DDR3 SA_DQ[14] DDR3...
  • Page 119 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQ[13] DDR3 SM_DRAMRST# DDR3 SA_DQ[20] DDR3 SA_DQ[11] DDR3 SA_DQ[17] DDR3...
  • Page 120 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SA_DM[2] DDR3 SA_DQ[19] DDR3 SA_DQS#[2] DDR3 SA_DQS[2] DDR3 SA_DQ[23] DDR3...
  • Page 121 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQS[3] DDR3 VTT0 SA_DQ[25] DDR3 VTT1 SA_DM[3] DDR3 SA_DQ[26] DDR3...
  • Page 122 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type VDDQ SB_MA[11] DDR3 SB_MA[14] DDR3 SA_MA[7] DDR3 SA_CKE[1] DDR3 SA_MA[11]...
  • Page 123 Processor Pin and Signal Information Table 8-48.rPGA988A Processor Pin Table 8-48.rPGA988A Processor Pin List by Pin Number List by Pin Number Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_CK#[0] DDR3 VTT0 SA_MA[4] DDR3 SB_MA[1] DDR3 SB_MA[3] DDR3 RSVD_TP...

  • Page 124: Table 8-49 Rpga988A Processor Pin List By Pin Name

    Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type BCLK DIFF CLK DMI_RX[0] BCLK_ITP AR30 DIFF CLK DMI_RX[1] BCLK_ITP# AT30...
  • Page 125 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type FDI_TX#[4] PEG_RX[13] PCIe FDI_TX#[5] PEG_RX[14] PCIe FDI_TX#[6] PEG_RX[15] PCIe FDI_TX#[7]...
  • Page 126 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type PEG_TX#[1] PCIe RSVD AJ15 PEG_TX#[2] PCIe RSVD AJ26 PEG_TX#[3] PCIe...
  • Page 127 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type RSVD_NCTF RSVD_TP RSVD_NCTF RSVD_TP RSVD_NCTF AP35 RSVD_TP RSVD_NCTF RSVD_TP RSVD_NCTF...
  • Page 128 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SA_DQ[12] DDR3 SA_DQ[48] DDR3 SA_DQ[13] DDR3 SA_DQ[49] AM10 DDR3 SA_DQ[14]...
  • Page 129 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SA_MA[4] DDR3 SB_DQ[0] DDR3 SA_MA[5] DDR3 SB_DQ[1] DDR3 SA_MA[6] DDR3...
  • Page 130 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type SB_DQ[36] DDR3 SB_DQS#[0] DDR3 SB_DQ[37] DDR3 SB_DQS#[1] DDR3 SB_DQ[38] DDR3...
  • Page 131 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type AN28 CMOS VAXG AR16 AT29 CMOS VAXG AR18 TDI_M AR29...
  • Page 132 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type AD33 AD34 AD35 AF26 AF27 AF28 AF29 AF30 AF31 AF32...
  • Page 133 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type VCC_SENSE AJ34 Analog AA10 VCCPLL AB26 VCCPLL AB27 VCCPLL AB28...
  • Page 134 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type AH27 AM14 AH28 AM17 AH29 AM20 AH30 AM25 AH31 AM27...
  • Page 135 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type Datasheet...
  • Page 136 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type VSS_NCTF VSS_NCTF AR34 VSS_NCTF VSS_NCTF AT35 VSS_NCTF VSS_NCTF VSS_NCTF VSS_SENSE...
  • Page 137 Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin Table 8-49.rPGA988A Processor Pin List by Pin Name List by Pin Name Buffer Buffer Pin Name Dir. Pin Name Dir. Number Type Number Type VTT0 AH11 VTT0 VTT0 AH12 VTT0 VTT0 AH14 VTT0 VTT0...

  • Page 138: Figure 8-21 Bga1288 Ballmap (Top View, Upper-Left Quadrant)

    Processor Pin and Signal Information Figure 8-21.BGA1288 Ballmap (Top View, Upper-Left Quadrant) Datasheet...

  • Page 139: Figure 8-22 Bga1288 Ballmap (Top View, Upper-Right Quadrant)

    Processor Pin and Signal Information Figure 8-22.BGA1288 Ballmap (Top View, Upper-Right Quadrant) Datasheet...

  • Page 140: Figure 8-23 Bga1288 Ballmap (Top View, Lower-Left Quadrant)

    Processor Pin and Signal Information Figure 8-23.BGA1288 Ballmap (Top View, Lower-Left Quadrant) Datasheet...

  • Page 141: Figure 8-24 Bga1288 Ballmap (Top View, Lower-Right Quadrant)

    Processor Pin and Signal Information Figure 8-24.BGA1288 Ballmap (Top View, Lower-Right Quadrant) Datasheet...

  • Page 142: Table 8-50 Bga1288 Processor Ball List By Ball Name

    Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball List by Ball Name Table 8-50.BGA1288 Processor Ball (Sheet 2 of 37) List by Ball Name (Sheet 1 of 37) Buffer Pin Name Pin # Type Buffer Pin Name Pin # COMP1 AD69 Analog...
  • Page 143 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 3 of 37) (Sheet 4 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type DMI_TX[3] GFX_VID[4]...
  • Page 144 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 5 of 37) (Sheet 6 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type PEG_RX#[7] PCIe...
  • Page 145 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 7 of 37) (Sheet 8 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type RSVD AP66...
  • Page 146 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 9 of 37) (Sheet 10 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type SA_DQ[19] BK15...
  • Page 147 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 11 of 37) (Sheet 12 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type SA_MA[11] BH30...
  • Page 148 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 13 of 37) (Sheet 14 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type SB_DQ[43] BT57...
  • Page 149 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 15 of 37) (Sheet 16 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type TRST# CMOS...
  • Page 150 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 17 of 37) (Sheet 18 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type VCAP1 AN39...
  • Page 151 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 19 of 37) (Sheet 20 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type VCC_SENSE Analog...
  • Page 152 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 21 of 37) (Sheet 22 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type VDDQ BB24...
  • Page 153 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 23 of 37) (Sheet 24 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type AC67 AA42...
  • Page 154 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 25 of 37) (Sheet 26 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type AH50 AH51...
  • Page 155 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 27 of 37) (Sheet 28 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type AU14 AY17...
  • Page 156 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 29 of 37) (Sheet 30 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type BB50 BK53...
  • Page 157 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 31 of 37) (Sheet 32 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type BU55 BU58...
  • Page 158 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 33 of 37) (Sheet 34 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type VSS_SENSE Analog...
  • Page 159 Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-50.BGA1288 Processor Ball List by Ball Name List by Ball Name (Sheet 35 of 37) (Sheet 36 of 37) Buffer Buffer Pin Name Pin # Pin Name Pin # Type Type VTT0 AN35...

  • Page 160: Table 8-51 Bga1288 Processor Ball List By Ball Number

    Processor Pin and Signal Information Table 8-50.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Name List by Ball Number (Sheet 37 of 37) (Sheet 2 of 37) Buffer Buffer Pin Name Pin # Pin # Pin Name Type Type VTT1 VTT1...
  • Page 161 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 3 of 37) (Sheet 4 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AA42 AB41...
  • Page 162 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 5 of 37) (Sheet 6 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AD26 VAXG...
  • Page 163 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 7 of 37) (Sheet 8 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AH12 VAXG...
  • Page 164 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 9 of 37) (Sheet 10 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AK66 RSVD...
  • Page 165 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 11 of 37) (Sheet 12 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AN46 VCAP1...
  • Page 166 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 13 of 37) (Sheet 14 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AU35 AW24...
  • Page 167 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 15 of 37) (Sheet 16 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type AY23 PEG_RX#[10]...
  • Page 168 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 17 of 37) (Sheet 18 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BB17 VDDQ...
  • Page 169 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 19 of 37) (Sheet 20 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BE64 SA_DQS[7]...
  • Page 170 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 21 of 37) (Sheet 22 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BK44 SA_DQS[4]...
  • Page 171 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 23 of 37) (Sheet 24 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BM70 BP35...
  • Page 172 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 25 of 37) (Sheet 26 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BT33 SB_MA[5]...
  • Page 173 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 27 of 37) (Sheet 28 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type BV33 SM_RCOMP[0]...
  • Page 174 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 29 of 37) (Sheet 30 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type PEG_TX#[5] PCIe...
  • Page 175 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 31 of 37) (Sheet 32 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type PEG_TX#[15] PCIe...
  • Page 176 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 33 of 37) (Sheet 34 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type PROC_DETECT PEG_RX#[3]...
  • Page 177 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball Table 8-51.BGA1288 Processor Ball List by Ball Number List by Ball Number (Sheet 35 of 37) (Sheet 36 of 37) Buffer Buffer Pin # Pin Name Pin # Pin Name Type Type VCAP2 RSVD...
  • Page 178 Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball List by Ball Number (Sheet 37 of 37) Buffer Pin # Pin Name Type VCCPLL VCCPLL VCAP2 VCAP2 VCAP0_VSS_SENSE VCAP0_SENSE DBR# DPLL_REF_SSCLK DIFF VCCPWRGOOD_0 Async CMOS TAPPWRGOOD Async CMOS Datasheet...

  • Page 179: Package Mechanical Information

    Processor Pin and Signal Information Package Mechanical Information Figure 8-25. rPGA Mechanical Package (Sheet 1 of 2) Datasheet...

  • Page 180: Figure 8-26 Rpga Mechanical Package (Sheet 2 Of 2)

    Processor Pin and Signal Information Figure 8-26.rPGA Mechanical Package (Sheet 2 of 2) Datasheet...

  • Page 181: Figure 8-27 Bga Mechanical Package (Sheet 2 Of 2)

    Processor Pin and Signal Information Figure 8-27.BGA Mechanical Package (Sheet 2 of 2) § Datasheet...

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