Deep Sleep State-State 6; Clock Control; Power And Ground Pins - Intel CELERON 1.10 GHZ Datasheet

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Intel Celeron Processor up to 1.10 GHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input. (See
be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum
assertion of one BCLK period.
2.2.6 Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK input be held low during the Deep Sleep State. Stopping
of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7

Clock Control

BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in the Sleep or Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache
will be restarted only after the internal clocking mechanism for the processor is stable (i.e., the
processor has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3

Power and Ground Pins

There are five pins defined on the S.E.P. Package for voltage identification (VID) and four pins on
the PPGA, FC-PGA, and FC-PGA2 packages. These pins specify the voltage required by the
processor core. These have been added to cleanly support voltage specification variations on
current and future Celeron processors.
For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 V
(power) and 30 V
voltage levels to the components. V
pins, while 4 V
For only the S.E.P. Package, one V
V
CC CORE
18
(ground) inputs. The 27 V
SS
CC CORE
inputs (1.5 V) are used to provide a AGTL+ termination voltage to the processor.
TT
CC 5
must remain electrically separated from each other.
Section 2.2.6.) Once in the Sleep state, the SLP# pin can
pins are further divided to provide the different
CC
inputs for the processor core account for 19 of the V
pin is provided for Voltage Transient Tools. V
CC
CC
and
CC 5
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