Related Manuals for Intel P4000 - 11-2010 SPECIFICATION
Summary of Contents for Intel P4000 - 11-2010 SPECIFICATION
- Page 1 Intel® Celeron® Mobile Processor P4000 and U3000 Series Specification Update November 2010 Document Number: 324456-005...
- Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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Page 3: Table Of Contents
Contents Revision History ......................4 Preface ........................5 Summary Tables of Changes..................7 Identification Information ..................14 Errata ........................17 Specification Changes....................43 Specification Clarifications ..................43 Documentation Changes ..................44 § Specification Update... -
Page 4: Revision History
Revision History Revision History Revision Version Description Date -001 -001 Initial Release March 2010 • Updated K-0 Stepping Microcode Update • Updated C-2 Stepping Microcode Update -002 -001 July 2010 • Fixed AAZ69 • Added Errata AAZ10S-11S • Added Errata AAZ96-AAZ99 -003 -001 August 2010... -
Page 5: Preface
ACPI Specifications www.acpi.info Notes: Documentation changes for Intel® 64 and IA-32 Architecture Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B, and bug fixes are posted in the Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Specification Update... - Page 6 Preface Nomenclature Errata are design defects or errors. These may cause the Intel® Celeron® P4000 and U3000 Mobile Processor Series behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.
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Page 7: Summary Tables Of Changes
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: Specification Update... - Page 8 Summary Tables of Changes Errata (Sheet 1 of 5) Steppings Number Status ERRATA AAZ1 No Fix The Processor May Report a #TS Instead of a #GP Fault REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May AAZ2 No Fix Use an Incorrect Data Size or Lead to Memory-Ordering...
- Page 9 Summary Tables of Changes Errata (Sheet 2 of 5) Steppings Number Status ERRATA Improper Parity Error Signaled in the IQ Following Reset When a AAZ21 No Fix Code Breakpoint Is Set on a #GP Instruction An Enabled Debug Breakpoint or Single Step Trap May Be Taken AAZ22 after MOV SS/POP SS Instruction If It Is Followed by an No Fix...
- Page 10 Processor LBR, BTM or BTS Records May Have Incorrect Branch From AAZ57 No Fix Information After an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive Thermal Throttling VMX-Preemption Timer Does Not Count Down at the Rate AAZ58 No Fix...
- Page 11 Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for AAZ68 No Fix Disabled Breakpoints This erratum is removed as it doesn not apply to the Intel AAZ69 Celeron P4000 and U3000 Mobile Processor Series Delivery of Certain Events Immediately Following a VM Exit May...
- Page 12 VM Entry May Omit Consistency Checks Related to Bit 14 (BS) AAZ102 No Fix of the Pending Debug Exception Field in Guest-State Area of the VMCS Intel Turbo Boost Technology Ratio Changes May Cause AAZ103 No Fix Unpredictable System Behavior Specification Update...
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Page 13: Specification Changes
Summary Tables of Changes Specification Changes Number SPECIFICATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None for this revision of this specification update. Documentation Changes Number DOCUMENTATION CHANGES None for this revision of this specification update. §... -
Page 14: Identification Information
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. The Intel® Celeron® P4000 and U3000 Mobile Processor Series can be identified by the following register contents:... - Page 15 Identification Information Component Marking Information The processor stepping can be identified by the following component markings: Figure 1. Intel® Celeron® P4000 and U3000 Mobile Processor Series PGA Component Markings For PGA – GRP1LINE1 (limited to 18 char, 13 pt font): INTEL{M}{C}’YY...
- Page 16 DDR3: 1066/800 MT/s Gfx: 667 MHz Notes: Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled. Core Tjmax = 105°C, Graphics Tjmax = 100°C Core Tjmax = 90°C, Graphics Tjmax = 85°C Standard voltage with 35-W TDP Ultra low voltage with 18-W TDP The core frequency reported in the processor brand string is rounded to 2 decimal digits.
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Page 17: Errata
Under certain conditions as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 18 Errata AAZ4. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in higher than expected values. Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than expected.
- Page 19 ENTER instructions. This erratum is not expected to occur in Ring 3. Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0. Intel has not observed this erratum on any commercially-available software. Workaround:None identified.
- Page 20 Errata AAZ11. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code.
- Page 21 Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially-available software.
- Page 22 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially-available software.
- Page 23 Operating System to observe higher processor utilization than actual, which could lead the OS into raising the P-state. During Intel TM1 activation, the OS P- state request is irrelevant and while on-demand throttling is enabled, it is expected that the OS will not be changing the P-state.
- Page 24 Errata Implication: Since Intel requires that Intel Thermal Monitor be enabled in order to be operating within specification, this erratum should never be seen during normal operation. Workaround:Software should not disable Thermal Monitor during processor operation. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 25 Errata Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAZ31. Two xAPIC Timer Event Interrupts May Unexpectedly Occur Problem: If an xAPIC timer event is enabled and while counting down the current count reaches 1 at the same time that the processor thread begins a transition to a low power C- state, the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0.
- Page 26 Errata Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR properly and may not generate an error interrupt. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAZ35. DR6 May Contain Incorrect Information When the First Instruction after a MOV SS,r/m or POP SS Is a Store Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused...
- Page 27 10B (All Including Self) or 11B (All Excluding Self). Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle the broadcast IPI. Intel has not observed this erratum with any commercially-available software.
- Page 28 Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 29 Errata Workaround:If the handler of the affected events inspects the arithmetic portion of the saved EFLAGS value, then system software should perform a synchronized paging structure modification and TLB invalidation. Status: For the steppings affected, see the Summary Tables of Changes. AAZ46.
- Page 30 PML4E or PDPTE Problem: On processors supporting Intel 64 architecture, the PS bit (Page Size, Bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
- Page 31 Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling. Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch "From" addresses for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E, or Adaptive Thermal Throttling. Workaround:None identified.
- Page 32 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: • Intel® Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
- Page 33 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially-available software.
- Page 34 DR7 is disabled. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAZ69. This Erratum is Removed as it Does not Apply to the Intel Celeron P4000 and U3000 Mobile Processor Series Problem: Implication: N/A Workaround:N/A Status: AAZ70.
- Page 35 Intel Turbo Boost Technology value will be returned for non-existent core configurations. Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel Turbo Boost Technology processor capabilities may report erroneous results. Workaround:It is possible for the BIOS to contain a workaround for this erratum.
- Page 36 Errata Status: For the steppings affected, see the Summary Tables of Changes. AAZ74. PCI Express x16 Port Logs Bad TLP Correctable Error When Receiving a Duplicate TLP Problem: In the PCI Express 2.0 Specification a receiver should schedule an ACK and discard a duplicate TLP (Transaction Layer Packet) before ending the transaction within the data link layer.
- Page 37 Implication: This erratum may cause unpredictable system behavior. Intel has not observed this erratum with any commercially-available software. Workaround:None identified.
- Page 38 Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset. Intel has not observed this erratum with any commercially-available software. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.
- Page 39 REP I/O instruction. Due to this erratum, the setting of the IO_SMI bit may be lost. This may happen under a complex set of internal conditions with Intel® Hyper- Threading Technology enabled and has not been observed with commercially available software.
- Page 40 Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events may be inaccurate. The degree of under or over counting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 41 SS.B bit is 1 and the adjustment will be to the 32-bit ESP register. Due to this erratum, the adjustment will incorrectly be made to the 16-bit SP register. Intel has not observed this erratum with any commercially available software.
- Page 42 Problem: When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different mount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic.
- Page 43 Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Problem: When Intel Turbo Boost Technology is enabled as determined by the TURBO_MODE_DISABLE bit being “0” in the IA32_MISC_ENABLES MSR (1A0H), the process of locking to new ratio may cause the processor to run with incorrect ratio settings.
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Page 44: Specification Changes
Specification Changes Specification Changes There are no, new Specification Changes in this Specification Update revision. § § Specification Clarifications There are no, new Specification Clarifications in this Specification Update revision. § § Specification Update... -
Page 45: Documentation Changes
Documentation Changes Documentation Changes There are no, new Documentation Changes in this Specification Update revision. Specification Update...