Bclk, Tck, Picclk Generic Clock Waveform At The Processor Edge Fingers; Bclk Signal Quality Guidelines For Edge Finger Measurement (For The S.e - Intel CELERON 1.10 GHZ Datasheet

® ®
Intel Celeron Processor up to 1.10 GHz
Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)
V1': BCLK V
V2': BCLK V
V3': V Absolute Voltage Range
IN
V4': Rising Edge Ringback
V5': Falling Edge Ringback
V6': T Ledge Voltage
line
V7': T Ledge Oscillation
line
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may dip back to after passing the V
guideline is an absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The
midpoint voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.
Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
V2
V1
54
T# Parameter
IL
IH
T3
V6
Min Nom Max
0.5
2.0
–0.5 3.3
2.0
0.5
1.0 1.7
0.2
(rising) or V
IH
V7
V5
V3
T6 T4
Unit Figure Notes
V 12
V 12
V 12 2
V 12 3
V 12 3
V 12 At Ledge Midpoint
V 12 Peak-to-Peak
(falling) voltage limits. This
IL
V3
V4
T5
Datasheet
4
5