Fsb Differential Clock Specifications (1600 Mhz Fsb); Fsb Differential Clock Specifications (1333 Mhz Fsb) - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

Electrical Specifications
Table 2-17. FSB Differential Clock Specifications (1600 MHz FSB)
BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew
Rate
Slew Rate Matching
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 400 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -100 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +100 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3. For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
4. In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5. Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
6. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
7. Duty Cycle (High time/Period) must be between 40 and 60%
Table 2-18. FSB Differential Clock Specifications (1333 MHz FSB)
BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2. The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3. In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
4. Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
5. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75 mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
6. Duty Cycle (High time/Period) must be between 40% and 60%.
Datasheet
T# Parameter
T# Parameter
Min Nom Max
397.962 - 400.037
2.499766 - 2.512800
- - 150
2.5 - 8
N/A N/A 20
Min Nom Max
331.633 — 333.367
2.99970 — 3.01538
— — 150
2.5 — 8
N/A N/A 20
Unit Figure Notes
MHz -
ns 2-3 2
ps 2-3 3, 4, 7
V/ns 2-4 5
% - 6
1
Unit Figure Notes
MHz - 6
ns 2-3 2
ps 2-3 3
V/ns 2-4 4
% - 5
33
1