Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 60

Table 4-2.
Land
Land Name
#
E7 RESERVED
E8
E9
E10
E11
E12 DSTBP1#
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23 RESERVED
E24
E25
E26
E27
E28
E29
F2 GTLREF2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23 RESERVED
F24 TESTHI7
60
Numerical Land
Assignment
Signal Buffer
Direction
Type
VSS Power/Other
D19# Source Synch Input/Output
D21# Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
D26# Source Synch Input/Output
VSS Power/Other
D33# Source Synch Input/Output
D34# Source Synch Input/Output
VSS Power/Other
D39# Source Synch Input/Output
D40# Source Synch Input/Output
VSS Power/Other
D42# Source Synch Input/Output
D45# Source Synch Input/Output
FC10 Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
FC26 Power/Other
Power/Other
BR0# Common Clock Input/Output
VSS Power/Other
RS1# Common Clock
FC21 Power/Other
VSS Power/Other
D17# Source Synch Input/Output
D18# Source Synch Input/Output
VSS Power/Other
D23# Source Synch Input/Output
D24# Source Synch Input/Output
VSS Power/Other
D28# Source Synch Input/Output
D30# Source Synch Input/Output
VSS Power/Other
D37# Source Synch Input/Output
D38# Source Synch Input/Output
VSS Power/Other
D41# Source Synch Input/Output
D43# Source Synch Input/Output
VSS Power/Other
Power/Other
Land Listing and Signal Descriptions
Table 4-2.
Land
Land Name
#
F25 TESTHI2
F26 TESTHI0
F27 VTT_SEL
F28 BCLK0
F29 RESERVED
G1 BPMb0#
G2 COMP2
G3 BPMb3#
G4 BPMb2#
G5 PECI
G6 RESERVED
G7 DEFER#
G8 BPRI#
G9 D16#
G10 GTLREF3
G11 DBI1#
G12 DSTBN1#
G13 D27#
G14 D29#
G15 D31#
G16 D32#
G17 D36#
G18 D35#
Input G19 DSTBP2#
G20 DSTBN2#
G21 D44#
Input G22 D47#
G23 RESET#
G24 TESTHI6
G25 TESTHI3
G26 TESTHI5
G27 TESTHI4
G28 BCLK1
G29 BSEL0
G30 BSEL2
H1 GTLREF0
H2 GTLREF1
H3 VSS
H4 FC35
H5 TESTHI10
H6 VSS
H7 VSS
H8 VSS
H9 VSS
H10 VSS
Input H11 VSS
Numerical Land
Assignment
Signal Buffer
Direction
Type
Power/Other Input
Power/Other Input
Power/Other Output
Clock Input
Common Clock Input/Output
Power/Other Input
Common Clock Input/Output
Common Clock Input/Output
Power/Other Input/Output
Common Clock Input
Common Clock Input
Source Synch Input/Output
Power/Other Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Common Clock Input
Power/Other Input
Power/Other Input
Power/Other Input
Power/Other Input
Clock Input
Asynch CMOS Output
Asynch CMOS Output
Power/Other Input
Power/Other Input
Power/Other
Power/Other
Power/Other Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
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