Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 66

Table 4-3. Signal Description (Sheet 3 of 10)
Name
D[63:0]#
DBI[3:0]#
DBR#
DBSY#
66
Type
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must
connect the appropriate pins/lands on all such agents. The data
driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group
of 16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals
to data strobes and DBI#.
Quad-Pumped Signal Groups
Input/
Output
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]#
signals are activated when the data on the data bus is inverted. If
more than half the data bits, within a 16-bit group, would have
been asserted electrically low, the bus agent may invert the data
bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Input/
Output
Bus Signal
DBI3#
DBI2#
DBI1#
DBI0#
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by
Output a debug port interposer so that an in-target probe can drive
system reset. If a debug port is implemented in the system, DBR#
is a no connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is
Input/
in use. The data bus is released after DBSY# is de-asserted. This
Output
signal must connect the appropriate pins/lands on all processor
FSB agents.
Land Listing and Signal Descriptions
Description
DSTBN#/
DBI#
DSTBP#
0 0
1 1
2 2
3 3
Data Bus
Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Datasheet