Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 46

Table 4-1.
Land Name Land #
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
A20M#
ADS#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
BNR#
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
46
Alphabetical Land
Assignments
Signal Buffer
Direction
Type
L5 Source Synch Input/Output
P6 Source Synch Input/Output
M5 Source Synch Input/Output
L4 Source Synch Input/Output
M4 Source Synch Input/Output
R4 Source Synch Input/Output
T5 Source Synch Input/Output
U6 Source Synch Input/Output
T4 Source Synch Input/Output
U5 Source Synch Input/Output
U4 Source Synch Input/Output
V5 Source Synch Input/Output
V4 Source Synch Input/Output
W5 Source Synch Input/Output
AB6 Source Synch Input/Output
W6 Source Synch Input/Output
Y6 Source Synch Input/Output
Y4 Source Synch Input/Output
AA4 Source Synch Input/Output
AD6 Source Synch Input/Output
AA5 Source Synch Input/Output
AB5 Source Synch Input/Output
AC5 Source Synch Input/Output
AB4 Source Synch Input/Output
AF5 Source Synch Input/Output
AF4 Source Synch Input/Output
AG6 Source Synch Input/Output
AG4 Source Synch Input/Output
AG5 Source Synch Input/Output
AH4 Source Synch Input/Output
AH5 Source Synch Input/Output
AJ5 Source Synch Input/Output
AJ6 Source Synch Input/Output
K3 Asynch CMOS Input
D2 Common Clock Input/Output
R6 Source Synch Input/Output
AD5 Source Synch Input/Output
F28 Clock Input
G28 Clock Input
C2 Common Clock Input/Output
AJ2 Common Clock Input/Output
AJ1 Common Clock Input/Output
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2 Common Clock Input/Output
AG3 Common Clock Input/Output
Land Listing and Signal Descriptions
Table 4-1. Alphabetical Land
Assignments
Signal Buffer
Land Name Land #
Type
BPMb0# G1 Common Clock Input/Output
BPMb1# C9 Common Clock Input/Output
BPMb2# G4 Common Clock Input/Output
BPMb3# G3 Common Clock Input/Output
BPRI# G8 Common Clock
BR0# F3 Common Clock Input/Output
BSEL0 G29 Asynch CMOS
BSEL1 H30 Asynch CMOS
BSEL2 G30 Asynch CMOS
COMP0 A13 Power/Other
COMP1 T1 Power/Other
COMP2 G2 Power/Other
COMP3 R1 Power/Other
COMP8 B13 Power/Other
D0# B4 Source Synch Input/Output
D1# C5 Source Synch Input/Output
D2# A4 Source Synch Input/Output
D3# C6 Source Synch Input/Output
D4# A5 Source Synch Input/Output
D5# B6 Source Synch Input/Output
D6# B7 Source Synch Input/Output
D7# A7 Source Synch Input/Output
D8# A10 Source Synch Input/Output
D9# A11 Source Synch Input/Output
D10# B10 Source Synch Input/Output
D11# C11 Source Synch Input/Output
D12# D8 Source Synch Input/Output
D13# B12 Source Synch Input/Output
D14# C12 Source Synch Input/Output
D15# D11 Source Synch Input/Output
D16# G9 Source Synch Input/Output
D17# F8 Source Synch Input/Output
D18# F9 Source Synch Input/Output
D19# E9 Source Synch Input/Output
D20# D7 Source Synch Input/Output
D21# E10 Source Synch Input/Output
D22# D10 Source Synch Input/Output
D23# F11 Source Synch Input/Output
D24# F12 Source Synch Input/Output
D25# D13 Source Synch Input/Output
D26# E13 Source Synch Input/Output
D27# G13 Source Synch Input/Output
D28# F14 Source Synch Input/Output
D29# G14 Source Synch Input/Output
D30# F15 Source Synch Input/Output
D31# G15 Source Synch Input/Output
Direction
Input
Output
Output
Output
Input
Input
Input
Input
Input
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