Features; Power-On Configuration Options; Clock Control And Low Power States; Power-On Configuration Option Signals - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

Features

6 Features
6.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for configuration purposes, the processor does not distinguish between
a "warm" reset and a "power-on" reset.
Table 6-1.

Power-On Configuration Option Signals

Output tristate
Execute BIST
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
NOTE:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not be asserted
during RESET#.
3. Disabling of any of the cores within a processor must be handled by configuring the
EXT_CONFIG Model Specific Register (MSR). This MSR allows for the disabling of a single
core per die within the processor package.
6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
power states.
Datasheet
Configuration Option
Figure 6-1
Table 6-1.
Signal
1,2
SMI#
A3#
A25#
BR0#
A[24:4]#, A[35:26]#
for a visual representation of the processor low
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