Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 62

Table 4-2.
Land
Land Name
#
M25
M26
M27
M28
M29
M30
N1 PWRGOOD
N2 IGNNE#
N3
N4 RESERVED
N5 RESERVED
N6
N7
N8
N23
N24
N25
N26
N27
N28
N29
N30
P1 DPSLP#
P2
P3
P4
P5 RESERVED
P6
P7
P8
P23
P24
P25
P26
P27
P28
P29
P30
R1 COMP3
R2
R3 FERR#/PBE# Asynch CMOS
R4
R5
R6 ADSTB0#
R7
R8
62
Numerical Land
Assignment
Signal Buffer
Direction
Type
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
Power/Other
Asynch CMOS
VSS Power/Other
VSS Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
VCC Power/Other
Asynch CMOS
SMI# Asynch CMOS
INIT# Asynch CMOS
VSS Power/Other
A04# Source Synch Input/Output
VSS Power/Other
VCC Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
Power/Other
VSS Power/Other
A08# Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
VSS Power/Other
VCC Power/Other
Land Listing and Signal Descriptions
Table 4-2.
Land
Land Name
#
R23 VSS
R24 VSS
R25 VSS
R26 VSS
R27 VSS
R28 VSS
Input R29 VSS
Input R30 VSS
T1 COMP1
T2 DPRSTP#
T3 VSS
T4 A11#
T5 A09#
T6 VSS
T7 VSS
T8 VCC
T23 VCC
T24 VCC
T25 VCC
T26 VCC
T27 VCC
T28 VCC
Input T29 VCC
Input T30 VCC
Input U1 TDO_M
U2 FC29
U3 FC30
U4 A13#
U5 A12#
U6 A10#
U7 VSS
U8 VCC
U23 VCC
U24 VCC
U25 VCC
U26 VCC
U27 VCC
U28 VCC
Input U29 VCC
U30 VCC
Output V1 MSID1
V2 RESERVED
V3 VSS
V4 A15#
V5 A14#
V6 VSS
Numerical Land
Assignment
Signal Buffer
Direction
Type
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other Input
Asynch CMOS Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
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