Fsb Decoupling; Voltage Identification - Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet

2.2.3

FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3

Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop
LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage
to be delivered to the processor VCC lands (see
specifications). Refer to
for each processor frequency is provided in
Note: To support the Deeper Sleep State the platform must use a VRD 11.1 compliant
solution. The Deeper Sleep State also requires additional platform support. For further
information on Voltage Regulator-Down solutions, contact your Intel field
representative.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in
Extreme Processor QX9000 Series and Intel
Q8000, and Q8000S Series Specification Update for further details on specific valid core
frequency and VID values of the processor. Note that this differs from the VID
employed by the processor during a power management event (Thermal Monitor 2,
Enhanced Intel SpeedStep
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages.
to the state of VID[7:0]. A '1' in this table refers to a high voltage level and a '0' refers
to a low voltage level. If the processor socket is empty (VID[7:0] = 11111110), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The processor provides the ability to operate while transitioning to an adjacent
VID and its associated processor core voltage (V
the load line. It should be noted that a low-to-high or high-to-low voltage state change
may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 2-4
The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in
and Table
16
Table 2-11
®
technology, or Extended HALT State).
and Figure 2-1as measured across the VCC_SENSE and VSS_SENSE lands.
2-4. Refer to the Voltage Regulator Design Guide for further details.
Chapter 2.6.3
for the DC specifications for these signals. Voltages
Table 2-3.
Table 2-3. Refer to the Intel
®
Core™2 Quad Processor Q9000, Q9000S,
Table 2-1 specifies the voltage level corresponding
). This will represent a DC shift in
CC
Table 2-3
Electrical Specifications
for V overshoot
CC
®
Core™2
includes VID step sizes
Table 2-3
Datasheet