Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 73

Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 10 of 10)
Name
VID[7:0]
VID_SELECT
VRDSEL
VSS
VSSA
VSS_SENSE
VSS_MB_
REGULATION
VTT
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_SEL
Datasheet
Type
The VID (Voltage ID) signals are used to support automatic
selection of power supply voltages (V
Regulator Design Guide for more information. The voltage supply
for these signals must be valid before the VR can supply V
the processor. Conversely, the VR output must be disabled until
Output
the voltage supply for the VID signals becomes valid. The VID
signals are needed to support the processor voltage specification
variations. See Table 2-1
must supply the voltage that is requested by the signals, or
disable itself.
This land is tied high on the processor package and is used by the
Output VR to choose the proper VID table. Refer to the Voltage Regulator
Design Guide for more information.
This input should be left as a no connect in order for the processor
Input to boot. The processor will not boot on legacy platforms where
this land is connected to V
VSS are the ground pins for the processor and should be
Input
connected to the system ground plane.
VSSA provides isolated ground for internal PLLs on previous
Input generation processors. It may be left as a No-Connect on boards
supporting the processor.
VSS_SENSE is an isolated low impedance connection to processor
Output core V . It can be used to sense or measure ground near the
SS
silicon with little noise.
This land is provided as a voltage regulator feedback sense point
for V . It is connected internally in the processor package to the
SS
Output
sense point land V27 as described in the Voltage Regulator Design
Guide.
Miscellaneous voltage supply.
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
Output provide a voltage supply for some signals that require termination
to V on the motherboard.
TT
The VTT_SEL signal is used to select the correct V
Output for the processor. This land is connected internally in the package
to V .
SS
§
Description
). Refer to the Voltage
CC
for definitions of these signals. The VR
.
SS
TT
to
CC
voltage level
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