Single-Ended Clocking Bsel[1:0] Implementation; Single-Ended Clock Bsel Circuit (133 Mhz) - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
4.2.2

Single-Ended Clocking BSEL[1:0] Implementation

In a LV Intel Pentium
source that does not support the VTT_PWRGD protocol, the normal BSEL frequency selection
process does not work. Since the clock generator is not compatible with dynamic BSEL assertions,
all BSEL[1:0] signals should not be connected together. Instead, the BSEL pins on the clock
generator should be pulled-up to 3.3 V through a 1 KΩ, 5% resistor. This strapping forces the clock
generator into 133 MHz clocking mode and will only support 133 MHz capable processors. In
addition, each BSEL[1:0] of each processor should be left unconnected. Figure 15 shows a diagram
of this implementation.
.
Figure 15. Single-Ended Clock BSEL Circuit (133 MHz)
Table 17. BSEL[1:0] Encoding
BSEL[1:0]
11
NOTE: All other BSEL[1:0] combinations are not supported.
28
processor 512K platform that uses single-ended (SE) clocking or a clock
III
NC NC
BSEL0 BSEL1
Processor 1
System Bus Frequency
133 MHz
3.3V
1KW
5%
NC NC
BSEL0
BSEL0 BSEL1
Clock Driver
Processor 0
3.3V
1KW
5%
BSEL1
Design Guide