Differential Clock Waveform; Fsb Differential Clock Specifications (800 Mhz Fsb) - Intel BX80571E5300 - Pentium 2.6 GHz Processor Datasheet

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Table 18.

FSB Differential Clock Specifications (800 MHz FSB)

BCLK[1:0] Frequency

T1: BCLK[1:0] Period

T2: BCLK[1:0] Period Stability

T5: BCLK[1:0] Rise and Fall Slew Rate

T6: Slew Rate Matching

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor core frequencies

based on a 200 MHz BCLK[1:0].

Duty Cycle (High time/Period) must be between 40 and 60%.

The period specified here is the average period. A given period may vary from this specification

as governed by the period stability specification (T2). Min period specification is based on -

300 PPM deviation from a 5 ns period. Max period specification is based on the summation of

+300 PPM deviation from a 5 ns period and a +0.5% maximum variance due to spread spectrum

clocking.

In this context, period stability is defined as the worst case timing difference between successive

crossover voltages. In other words, the largest absolute difference between adjacent clock

periods must be less than the period stability.

Measurement taken from differential waveform.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured

using a ±75 mV window centered on the average cross point where Clock rising meets Clock#

falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to

use for the edge rate calculations. Slew rate matching is a single ended measurement.

Figure 3.