Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Datasheet page 69

Land Listing and Signal Descriptions
Table 4-3. Signal Description (Sheet 6 of 10)
Name
ITP_CLK[1:0]
LINT[1:0]
LOCK#
MSID[1:0]
PECI
PROCHOT#
PSI#
Datasheet
Type
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system
board. ITP_CLK[1:0] are used as BCLK[1:0] references for a
Input
debug port implemented on an interposer. If a debug port is
implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate
pins/lands of all APIC Bus agents. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt request signal,
and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI
are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Input
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to
the end of the last transaction.
Input/
Output
When the priority agent asserts BPRI# to arbitrate for ownership
of the processor FSB, it will wait until it observes LOCK# de-
asserted. This enables symmetric agents to retain ownership of
the processor FSB throughout the bus locked operation and
ensure the atomicity of lock.
On the processor these signals are not connected on the package
(they are floating). As an alternative to MSID, Intel has
Output implemented the Power Segment Identifier (PSID) to report the
maximum Thermal Design Power of the processor. Refer to
Section 2.5 for additional information regarding PSID.
Input/ PECI is a proprietary one-wire bus interface. See
Output details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
Input/ This indicates that the processor Thermal Control Circuit (TCC)
Output has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#.
See Section 5.2.4
Processor Power Status Indicator Signal. This signal may be asserted when
Output the processor is in the Deeper Sleep State. PSI# can be used to improve
load efficiency of the voltage regulator, resulting in platform power savings.
Description
for more details.
Chapter 5.3 for
69