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Line Adapter Status (LASTAT)
MOM 4- 47
1101* 0
1
2
3
4
5
6
7
Sync
Clr to send off
Data set rdy on
Sync Char trap
Char overflow
Char phase
1-sec timeout
trap
3-sec timeout
trap
Sync chain trap
Start/StOF
Clear to send off
Data set ready on
TC type II/I
Type TTY/IEM
'Iransrri t latch
Transmit line
trigger Cmrk/sp)
Line quiet; recv
line (mark/space)
Telegr line ad:Ftr
Dial In (DILIN)
MOM
4-47
1110*
0
1
2
3
4
5
6
7
Not
P~r
Indicator en (PwI)
Not Al:andon Call and Retry (ACR)
Not Present Next Digit (PND)
Not Digit Present (DPR)
Not call Reqst (CRQ) ; er Net Diag
NBRB ( i f DPR on)
Not Dia 1 NBR 4 ( diag)
Not Diag NBR2 (diag)
Valid address; dial NBRl (if DPR
on)
General Status (GS'IA'Il
MOM
4-47
1111* 0
1
2
3
4
5
6
7
Sync trap
Start/stop chain trap
Start/stop Data set ready trap
Dial trap
Start/stop char trap
'Iiroecut update trap
Timeout remettter
*
'Ibese eight fields tested with Branch on
Condition or Branch on Mask ccntrcl
words.
External Field Definitions, Communication
ModEt (,CPU TO EXT)
OCOO
Unassigned
0001
Unassigned
Storage Prctect 0
0010
0
~'!PO
bit
1
STPO l:it
2
S'IPO bit
3
STPO tit
4
STPO bit
5
STPO tit
6
STPO bit
7
S'IPO l:it
(STPO)
0 CQO)
1 (Ql)
2
(Q2)
3
(Q3)
4
(Q4)
5 ( Q5)
6
(Q6)
7
(Q7)
storage Protect 1 (STP1)
0011
0
STPl bit 0 (QO)
1
ST Pl bit 1 (Ql)
2
STP1 bit
2
(Q2)
3
STPl bit
3
(Q3)
4
STPl bit
4
(Q4)
5
STPl bit 5 (Q5)
6
STPl bit
6
(Q6)
7
STPl l::it 7 (Q7)
0100
Unassigned
Communications Adptr Diag Register (CADR)
0101
0
Bit trap check
1
General trap
2
First priority-check trap
3
4
5
6
7
0110
Unassigned
comrrunicaticns Parity Check (PARCIO
0111
0
Data l::it 0
1
Data bit 1
2
Data bit 2
3
Data tit 3
4
Data bit
4
5
Data bit 5
6
Data bit 6
7
Data bit 7
1000
Unassigned
Line Adapter Diag Register <IADR)
Sync
Start/StOQ
1001
0
Sync Diag ctls
Adpt Grp Test Ocs
1
Gate A-Reg DAIN Adpt Grp Test Ocs
2
Gate B-Re\DAIN
3
Gate 'IRCR
o DAIN
4
Gate Diag Stat-DAIN
5
Recv data rr.ark diag
6
select diag cleck
7
Diag clock
1010
Unassigned
Data Out ( DAOU'I)
1011
0
Cata out bit 0 (sync>
1
Data out bit 1 (sync>
2
Data out bit 2 <sync)
3
Data out bit
3
<sync)
4
Data out bit
4
C sync>
5
Data out bit
5
(sync)
6
Data out bit 6 (sync)
7
Data out bit 7 (sync)
2025 FEMM (7/69) 1-57
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