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-+J
A
j.--
Direct Control Bus Out
I
I
(Data from Storage 8 Bits)
+.---!,-------------
(Static Signals)
I
./I
I/
/
I
_____
_/,
-------------
I
I
I
I+-
s
~
r-
u
..J
I
I
f----
H
---i
i--c
I
I
I
I
I
I
I
I
I
Write Out (Pulse)
I
I
I
I
I
I
I
I
I
I
I
.. 1.
I
1•
I
L
I
p
. .
,
I
I
I
I
I
I
I
I
I
D~
1---J
•I
~E
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Timing Signal Bus Out
I
I
I
I
I
(Bits 8-15 of instruction)
I
I
I
(Pulses)
Read Out
(Pulse)
A. B.
C.
D. E. f. G
H.J. K
L. M. N
B. D
F. D
s
u
T
P.
Q.
R
Figure 4-15 ..
4-16 (7/69)
I
I
I
I
I
I
1~ I
M
..
,.
I
I
I
I
F__J
I
I
r---
K
..
,
'4--G
I
I
I
I
I
I
I
I
I
I
I
I
y
N
I
I
I
I
I
I
,.
N
I
..
,.
I
----r
~
Maximum transition time is
200
nsec.
Minimum duration is
500
nsec.
Maximum including transition.
100
ns.
Leading edges coincidental within skew tolerances
Leading edges coincidental within skew tolerances
Q
·'
I
I
I
I
I
I
I
I
/
I
I
R
. .
,
Overlap start Write Out to change D.
C.
P. O.
100
nsec. (MIN)
Overlap change of D.
C.
P. 0 to finish of Write Out
100
nsec. (Ml N)
Earliest time to sample hold I ine during read direct.
Minimum down time between pulses is
500
nsec.
Direct Control Signals Originating within the CPU
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