IBM 2025 Maintenance Manual page 216

Direct Control Bus In
(External Data 8 Bits)
(Static Signa Is)
Hold In
(Not Necessarily A Pulse)
External Signal Bus In
(Up to 6 Lines)
(Pulse)
A. B. C. K. L.
D
E
F
G
H
J
M
K
A
-I i.---
1
I
I I
ix_:--------
- - -- __ v . . . . .
1 _ _ _ _ _ _ _ _ _ _ _ _
I
I I
I I
I I
~F-1
!--G-i
I
I
I I
I•
D-----1 .....
I
I
1,,------------
I
I
I
I
I
I
I
,
..
H
I
I
I
I
I
I
I
..
,
i--c
I
I
I
I
I
I
I
~E
I
I
r-L
I
I
I
1------ - ---------
-----1-
1 I
I
I
I
---J
I
I
I
I
I
I
I
I
I
I
1..
J
I
M----J
No minimum transition duration specified
Minimum is 500 nsec. no maximum specified
Minimum is 500 nsec. no maximum specified
Minimum overlap between data change. 100 nsec. no maximum specified
Minimum overlap after data change. 100 nsec. no maximum specified
Minimum duration 500 nsec.
Maximum including transition 1000 nsec.
Minimum down level between pulses not specified
Figure 4-14. Direct Control Signals Originating Outside the CPU
2025 FEMM (7/69) 4-15