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Bl/SO
T4
+2Y
+Y Sel
T5
+2Y
T6
Figure A-3.
Basic Storage Cell
BO/Sl
T3
-X
Sel
of Tl and T3 is 2.8 volts while the base of
T2 and T4 is 2. 2 volts.
A.1.2.1.2 Read Operation:
To
read
information from the cell requires the
coincidence of x- and Y-voltage pulses.
The x-voltage at the base of T6 is
decreased from 2.6 volts to .7 volts while
the Y-voltage at the base of T5 is
increased from 0 volts to 1.7 volts.
Thus,
T6 is turned off and T5 is turned on.
Due
to the state of the flip-flop, T3 is
enabled and the sense current, which is
determined at the emitter of TS, flows to
BO.
In the case of a 0 being stored, the
state of the flip-flop is reversed and T4
is enabled.
A. 1 .• 2. 1. 3 Write Operation:
To write into
the cell requires the coincidence of X, Y,
and either BO or Bl.
Assuming a 1 is
stored in the cell and a 0 is to be
written, transistor Tl is on and transistor
T2 off.
The base of Tl and T3 is at 2. 8
volts.
The x- and Y-lines are pulsed as
previously indicated for a read cycle.
BO
is decreased from 5 volts to approximately
1.5 volts..
With the collector voltage of
T3 reduced to saturation level., the enabled
transistor T3 conducts all of its emitter
current through the base and pulls down the
collector voltage of transistor T2, which
in turn tends to turn off transistor Tl.
As Tl turns off, its collector voltage
rises and turns on T2.
At the completion
of this process a steady-state condition is
reached with Tl off and T2 on.
Thus, the
saturating flip-flop is in its opposite
condition and the 0 is stored in the cell.
A .• 1. 3 STORAGE MODULE
The storage module is a one-half inch by
one-half inch module consisting of a single
substrate with twenty-three SLT
input/output pins and eleven interstitial
Cf eed through) pins.
Two 64-bit chips arranged in an SY
bf
8X
by
1-bit configuration are mounted on the
substrate making the module organization 64
by
2 bits.
Nominal power dissipation per
module is approximately 275 mw.
A.1. 2.1 Cell
A.1.4 PERIPHERAL CIROJITS (FIGURE A4)
A.1. 2 .. 1.1 Steady-State Operation:
In
Figure A-3 .• the inboard transistors Tl and
T2 form a direct-coupled saturating
flip-flop.
Under steady-state conditions,,
one transistor is saturated with a
collector voltage of approximately 2 .• 2
volts While the other is cut off with a
collector voltage
Of
approximately 2.8
volts.
Assuming a 1 is stored in the cell,,
transistor Tl is on and T2 off.
The base
X-Drivers:
The X-driver is similar in
configuration to the SLD100 AOI circuit
except that i t is clamped out of
saturation.
The driver input is a two-way
AND circuit.
'!here are four drivers per
module and four load resistors per R-pack.
Y-Drivers:
The Y-driver is a saturating
emitter follower.
It has one input and
cannot be used as an AND circuit.
There
2025 FEMM (7/69)
A-3
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