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Section 1 E. Channel Procedures
2.52 MULTIPLEXER CHANNEL DEVICE ADDRESSING
The mul tii;:lexer channel address .<eight
high-order bits of the 16-bit address> is
00 hex.
Device addressing en the
rrultiplexer channel depends upon how a
device and its control unit operate with
the channel.
The Model 25 multiplexer
channel has 32 subchannels, each cf which
is associated with an individual device
address.
For devices that have their own
central unit self-contained, and fer
ccntrol units that operate two or more
devices simultaneously (such as the 2821),
individual subchannel addresses are
assigned to each device.
These addresses
are designated with a 0-bit in the
high-order position of the device address.
All of the 32 subchannels can be assigned
to individual control units using the
addressing
sho~n
in Figure 2-9.
Subchannel
Device Address
(UCW)
Binary
Hex
0
0000 0000
00
to
to
to
31
0001 1111
1F
Figure 2-9.
subchannel Addresses
For a third class of control units that
can operate two or more devices of which
only one can operate at a time, a single
subchannel can be used with a special
addressing scheme.
The first eight
subchannels also can te addressed and
operated as shared subchannels.
In this
case, the 0-tit position of the device
address is set to 1.
The rerraining three
bits of the high-order cyte are used to
designate the subchannel instead of the
normally used three tits in the low-order
byt~.
The bits of the low-order byte are
then used to designate the device address.
The comparatle addresses for use of the
subchannel as individual control unit and
as shared control unit are shown in Figure
2-10.
In
assigning device addresses, be
careful that a single subchannel is not
addressed by both its individual address
and by its shared address.
If this were to
hai;pen, the operation data in the
ucw
could
be accessed by both device ci;:eraticns and
result in transmission errors for both
devices.
In addition these addresses
shruld not te assigned to any of the
integrated
I/O
devices assigned tc channel
0 in a rranner that would prevent the use cf
a
UCW
as either in<li vi dual or shared.
An
example of this lockout would be the
addressing the 2540 Reader as 01 and the
2540 Punch as 9X.
Any atterrpt to use
either of these addresses for channel
devices would result in cperating either
the reader or punch of the 2540.
The
channel UCW-1 could not be used for the
channel tecause the 2540 is selected first.
The integrated I/0 devices have their own
UCWs.
Individual
Shared
C.U. Address
C.U. Address
ucw
Binary
Hex
Binary
Hex
0
0000
0000
00
1000
xx xx ax
1
0000
0001
01
1001
xx xx
9X
2
0000
0010
02
1010
xx xx
AX
3
0000
0011
03
1011
xx xx
BX
4
0000
0100
04
1100
xx xx ex
5
0000
0101
05
1101
xx xx
DX
6
0000
0110
06
1110
xx xx
EX
7
0000
0111
07
1111
xx xx
FX
Sharn
Bit~
:!=:J
IJ
T
UCW Address Bits
Device Address
Figure 2-10.
subchannel Addresses
Individual and Shared Control
Unit
2. 53 SELEC'IOR CHANNEL DEVICE ADDRESSING
The selector channel address (eight
high-order tits of the 11-bit address> is
01 hex.
Device addressing en the selector
channel may in theory be any of the 256
possible bit corrbinaticns.
The addressing
is limited at two points by the integrated
disk storage devices that are also assigned
to channel 1 and addresses 9X (Hex>.
The
value of X ranges from 0 to 3 for the four
possible disk drives.
The remaining
addresses have no special significance in
the processing unit, and rray be assigned as
required
l:y
the
prog~am
for the selector
channel devices.
2.54 CHANNEL AND UNIT ADDRESSING
RESTRICTICNS
No more than one addressing bit structure
can be assigned tc
a
si;:ecific
I/O
unit.
Also, the same unit address may not be
assigned to two or roore devices.
2.54.1 CHANNEL 1
When the BURSTCH (selector channel) core
load is loaded, device addresses 00 through
2025 FEMM (7/69)
2-37
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