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Section 2. Features
4.17 EXTERNAL INTERRUPTION AND DIRECT
CON'l'ROL FEATURES
The external interruption and direct
control features are combined here because
installation of the direct control feature
requires that the e xte rna 1 i nte rru pti on
feature also be installed.
The external
interruption feature,, however, can be
installed without the direct control
feature.
Both features are plugged on board
Al-A3.
4.17.1 SPECIFICATIONS
Signals on the direct control interface are
of three types:
1.
The direct-control bus-out and the
direct-control bus-in lines carry
static levels that remain on the lines
until changed
by
the CPU program or by
the external equipment.
2.
The timing-out, read-out, write-out,
and external bus-in lines carry pulses.
3.
The hold-in line may carry either a
pulse or a static signal.
These signals are shown in Figures 4-14
and 4-15.
In these figures,, all pulses are
coraidered positive and the up-level is
considered a logical one.
When the CPU power is off, all outputs
to the outbound busses or tag lines must be
at a logical zero.
4.17.2 AnJUSTMENTS
Although circuit adjustments cannot be made
to these features, the circuit cards of any
given type must operate satisfactorily in
any socket location specifying that type.
Selection or interchange of cards to obtain
satisfactory performance is unnecessary and
should not be done.
4.U INTERVAL-TIMER ADJUSTMENT
The singleshot located at A-A3J7 must be
adjusted as follows.
Scope the signal at
A-A3H3D05 CCT011).
Adjust the singleshot
to give a 10-millisecond
±
10% positive
going pulse at this point for 60-cycle
machines, or an 11-millisecond
±
10%
positive going pulse for 50-cycle machines.
It is not necessary to have the CPU clock
running to make this adjustment.
The
singleshot must be functioning all the time
power is on.
4-14 (7/69)
4.18.1 SERVICE CHECK AND CHECKOUT PROCEDURE
To test the interval-timer feature, first
run microdiagnostic *200.
Timer switch
must be on to run this test.
Next place
the machine in single-cycle mode and press
system reset.
Display the interval-timer
register; it must be zero.
Now alternately
press start and then display the
interval-timer register.
Each time this is
done, there is a 503 chance that the
register will be advanced..
Each time it
does advance, it is increased by only one
count.
When a count of one has been
reached, turn the interval-timer switch
off.
The interval-timer register should
continue to advance.
When all bi ts of the
C-register are on (interval-timer register
equals 15
>,
press the start button ten more
times.
'!he value in the interval timer
must not change.
Leaving the interval-timer switch off
and the machine in sing le-cycle mode, press
system reset.
Display the interval-timer
register; i t must be zero.
Press start ten
times.
The interval-timer register must
still be zero.
4.19 STORAGE PROTECTION FEATURE ADJUSTMENI'
Figure 4-16 shows the time relationship of
the STP1 local storaqe compared to the CPU
word type 2.
A delay line is used to
adjust the S'IP local storage read line.
This delay line has a tolerance of
+
3 to -2
nanoseconds and can be adjusted by using
the following procedure.
1.
Store the storage word 5210, followed
by an unconditional branch back to this
word, into an unused portion of control
storage.
Example:
Address
Contents
0280
5210
(FE Trap Area)
0282
8280
2.
Sync on word type 2 (location OlA -
B1C7B03).
3.
Scope and record the duration from the
10% rise
of •
YO ADDR LINES STP1. to the
10% fall of 'STP1 READ LINE' (ALO -
XQ007).
4.
The duration (Figure 4-17} must be
between 27 ns and 37 ns.
If this
requirement is not met, the delay line
must be plugged to satisfy this
condition.
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