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8 X Lines
Sense
Amps
:z
/I
.----
Bit
1
~
8 Y Lines
8Y
8Ylines
t - - -
Drivers
~
8
Bit 2
L/
0
7
4.,__
t - - -
Bit
Bit 3
Drivers
4..,__
Bit
1
t - - - - 1
~
Bit
4
Bit
TP
~~
1-----1
t------1
Bit 2
Bit 5
1 - -
~
-~
Bit 3
t------1
Bit
6
i - - -
I -
4~
Bit
4
10
t - - - - - '
Bit
7
1 - -
1 - -
4~
Bit 5
t - - -
Bit 8
i - - -
1 - -
4..._,
Bit
6
I - - -
Bit 9
1 - -
~~
1 - -
4~
Bit
7
I - - - -
Bit
10
1-----1
1-----1
4~
Bit 8
v
..._____..
1-----1
1-----1
Bit 9
1-----1
Bit
10
1-----1
v
1-----1
-
1-----1
$.
A.
Gate
(Read)
Figure A-2. Local Storage and Storage Protection Addressing
A.1.2 CIRCUIT OPERATION (FIGURE A-2)
An address is selected in the array with
the
c~incidence
of a positive Y-line and a
negative X-line.
This condition selects
10
storage cells., one in each bit or plane.
Selection of a cell causes current to flow
in either the bit-one sense zero-line or
the bit-zero sense-one line, depending on
the st ate of the storage cell.
The
differential sense amplifier, when gated.,
pr011ides an output indicative of the
polarity of the input.
For the selected cell to be written
into, the bit-one or bit-zero driver is
turn·ed on, depending on input data.
The
cell is left in the appropriate state when
the bit driver is turned off.
A-2
( 7/69)
Because the array module cannot be
powered directly from +6 volts, circuitry
on the card provides the proper levels (+2
volts and approximately 3.25 volts}.
There are two parts to the regulator
circuitry:
1.
a two-volt shunt regulator, and
2.
a series-dropping resistor.
The regulator amplifier absorbs the load
change while a resistor in parallel with it
conducts the major portion of the airrent.
The series-dropping resistor provides a
voltage drop from +6 volts to approximately
3.25 volts.
The storage latches are
connected (all in parallel} between
+2
volts and 3. 25 vol ts.
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