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3-3. CPU OPERATION
3-3-1. ROM Access
The ROM space is accessed in either of two cases.
The first
occurs after a CPU reset is canceled when the reset vectors
are fetched.
The second is when ROM monitor is being
executed.
The first is a function identical to that used in 68000 type
CPUs.
It is a cycle to fetch the interrupt stack addresses
for all addresses for the first command executed after the
CPU reset is canceled.
Bytes 0 to 4 of each address are the
stack address and the next four bytes are the command
address.
The second is a cycle carried out when commands written in
ROM are read.
The first ROM address is $eOOOOOOOO.
For either cycle, the ROM data width is only 8 bytes.
Therefore, to access long words (32-bit) four readout cycles
are required and for words (16-bit) two cycles.
A flowchart
of the various cycles is given below.
WSC-CDECR outputs the ROM access signal (ROM) when PORT
output from WSC-MEMC is "L" and addresses A22, A23 and A24
are all
"L"
MEMC outputs PORT in either of two cases: 1)
ROMDIS is "H" and AS is "L" 2) ROMDIS is
"L"
A29 is "H" and
A28 is
"L"
1) is for a reset vector fetch and 2) for normal
ROM access.
WSC-CDECR is output from ROMDIS.
It can be either "H" because
of a reset signal, or "L" when "l" is written to the CDECR
NVVS-1510/1530/1580
3-5
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