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3-3-5.
DIP Switch, ID-ROM
and
INT-STAT Access
These devices are connected to the I/O bus (IOD7 - IODlO),
but the chip select signal is output by WSC-CDECR.
DSACK
signals output to the CPU are also issued
by CDECR.
The
chip select signal is DIPSWROM, but address bits 7 and 8 are
re-decoded and allocated to the various !Cs.
A flowchart of this process is given below.
<CPU>
DIPSWROM address output
R/W =output
FCO - 2 output
SIZO, 1 = output
,___AS~=_o_s_=~"L_"__.J
<MEMC>
1 - - - - - - .....
-.i{
PORT output
l
< CDECR >
T.__ __ -.i{
DIPSWROM output]
1
~
IOA8, 9
=
"00"
-->
IDROM
(M87114L - IC63)
IOA8, 9
=
"10"
-->
INT-STAT
(LS540 - IC50)
..
-1"
-->
DIP-SW
<PARK>
IOBSEL output
Chip select output
~
IOD buffer
enabled
IOA8, 9 =
(LS541 - IC51)
~1
CS enabled
Data read/ write
f
IORD/WR output
J
--
- - - -
-- -
-
--- ---
- - - - - - - - -
-
- -
- - -
-
-
-
-
-
- - - - - -
-
-
-
-
- -
-
-
-
-
---
- -
-
-
-
--
- - -
-
---
-
-
-- -
-- -
-
- -
- -
-
-
-
-
-
--
_.,....
1/0
DSACKO
f
DSACKPT output J
r
As
=
os
=
"H"
1
.__ __ _..,I
PORT negated
I
I
DIPSWROM negated/
DSACKPT negated
l
IOBSEL negated/
IORD/WR negated
f
T
r
End of cycle
]
NWS-1510/1530/1580
3-13
I
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