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used for this operation is called burst transfer.
A normal
memory access requires a minimum of 3 clocks (5 in the case
of the 1500 because it operates with two wait states).
A
burst transfer to the cache, however, operates as follows. If
no wait state intervenes, four long words can be accessed
within 5 clocks.
In the case of the 1500, the first long word
needs two wait states and the subsequent three words one each
for a total of 10 clocks.
In the PWS-1500, this function is implemented using circuit
built into WSC-MEMC on the MPU-7 board and the main memory's
high-speed page mode read cycle.
The high-speed page mode
read cycle is a DRAM special function as shown below.
RAs\ ________ /
CAS
Address
ROW
Data O u t - - - - - - - - -
In other words, RAS is maintained "L" in the same lower
address, and each time the column address is switched CAS is
input, causing data from continuous addresses to be read.
A flowchart of the process when the CPU issues a burst
transfer request (CBREQ) is given below.
NWS-1510/1530/1580
3-31
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