Table of Contents
Advertisement
When the CPU accesses main memory, selector A switches from
CPU to MA and the DMAC data line is opened.
CPA
CPU
CPD
MA
MEMORY
MD
RAS
DMAC
CAS
High impeadance
MEMC
The same type of bus can be used when the CPU accesses DMAC.
However, when RAS/CAS are not output from MEMC, CPD switches
to MD(DMA) when writing data to DMAC, and from to MD(DMA) to
CPD when reading data.
IOA is for specification of DMAC
register addresses, RWO is for read/writes and DSACKDMA2 is
for DSACK from DMAC.
The bus used by the CPU to access DMAC is the same type as
that it uses to access main memory.
Therefore, arbitration of
bus usage is necessary between the CPU and DMAC memory.
For
this purpose, a MDA2 access decode signal is input to DMA,
and BGV is output when main memory arbitration has been
obtained.
The logical product of DMA2 and BVG is input to the
DMAC
cs.
BVG is also input to buffer D to initially enable
it.
A flowchart of this process is given below.
3-10
NWS-1510/1530/1580
Advertisement
Table of Contents
