Sony NWS-1510 Service Manual page 69

Net work station
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Register
Register name
RO
Total number of horizontal character
Rl
Number of horizontal characters displayed
R2
R3
R4
RS
R6
R7
RS
R9
Ra
Re
Rd
Rlb
Rle
Horizontal sync position
Sync pulse width
Total number of vertical characters
Total raster adjust
Number of vertical characters displayed
Vertical sync position
Interlace and skew
Maximum
Cursor 1 start raster
Starting address 1 (high)
Starting address 1 (low)
Vertical sync position fine adjustment
Control
Setting unit
chrl6 pixel
chr
chr
chr
line
raster
line
line
raster
mem adrs
mem adrs
raster Ox3
Setting value
unitOxSl
Ox40
Ox48
Ox33
Ox64
OxS
Ox60
Ox60
OxlO
address
0
0
10x8
See the HD6445 user's manual for the meanings of parameters, bit positions, etc.
(3) Setting data sent to the HD6445
First the raster number for the desired address register setting is read in. Next,
the setting for the data register is read in.
This ensures that data is read into the designated register. Data may be read out of
readable registers in the same way.
Example: Setting register R6 to 128
1 Write 6 to the address register.
2 Write 182 to the data register.
3 Completed.
The default setting for the address register is Oxf0fc2000 and that for the data
register is Oxf0fc2001.
(4) Color palette
Arn81C458
(Bt548)
is a video D/A converter incorporating 256 x
24 bits of color
palette RAM.
The DSC - 008 has a
8 - frame frame buff - er,
allowing simultaneous
display of 256 colors
from a palette of 16. 7 million.
Like the CRTC,
the color
palette has data and control registers which allow programming as described in (3)
above. The normal setting for the address register is Oxf0fc4000 and for the data
register is Oxf0fc4004.
See the data sheet for a detailed description.
3-9-4. Status registers
The status registers are at the address shown in 12.2 (2). See Fig. 1.
(page 3-44, 3-45)
Status registers
(Read)
Bit 0: If the req signal status is 1, a read/write is being executed in the frame
buffer ( FB).
Bit 1: If the exec signal status is 1, a command is being execut - ed in the frame
buffer (FB). The relation of this signal to the req signal is as follows:
req exec
0
0
Idle
0
1
Waiting for command to execute.
1
0
Waiting for read/write (read/write command to FB, mask command).
3-42
NWS-1510/1530/1580

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