Sony NWS-1510 Service Manual page 74

Dot mask register:
Mask used when writing single pixels.
It is set to Oxdfff to write to the third pixel of the word.
3-9-6. DSC- 008 circuit board block diagram
FIFO:
A one - stage FIFO is provided for raster operation commands and data. It allows
asynchronous operation in order to cut the host's waiting time to a minimum.
Raster operation cycle controller
This controller overseas FB read/write operations based on com-mands and CRTC from
the host. The three main controller states are idle, display and command execution.
The display status consists of FB refresh and send display ad - dress cycles. The
controller is synchronized with H - sync during display operation and interrupts are
given higher priority than
during command execution status. In command execution status there is a wait of two
memory cycles.
Command execution status is the condition under which commands from the host are
executed. Available operations are copy within plane (Copy), copy between planes
(PCopy), write to plane (HWRite) and read from plane (HRead).
The controller is in idle status when not in one of the states described above.
Address controller (uPD6501G - 160):
Addresses needed to execute commands are maintained in gate array uPD6501G- 160. The
addresses needed to define the source and destination rectangles are as follows:
source rectangle X address (SRXA), source X address (SXA), source Y address (SYA),
destina-tion rectangle X address (DRXA), destination X address (DXA), destination Y
address (DYA). The difference between the rectangle X address and X address is that,
while the rectangle X address is the X address of the rectangle, the X address is
the FB address actually used for read/write operations.
These addresses are set, incremented ~r reduced, and altered (SRXA (DRXA) is loaded
into SXA (DXA)) in command status.
Raster operation chip (WSC - SBLT):
An
up - graded version of the CXD1029 used in the NWB - 225A, this chip shifts data
read from the FB and performs Boolean logic operations. The CXD1029 was capable of
handling a single plane, but the WSC- SBLT can handle two planes at once.
RAMDAC (Am81C458 - SOJC):
This device converts video data read from 8 - frame memory into 24 - bit form using
its built- in color palette and drives the display monitor.
Fig. 3 is a block diagram of the DSC- 008 circuit board.(page 3-59, 3-60)
3-9-7. Host interface/FIFO
Two PAL's are used to decode addresses and for ACK and FIFO
control. The decode signal meanings are as follows:
/ROPAS: Raster command (decodes AS only)
/ROPDS: Raster command (AS and DS)
/CTRL: Control port, CRTC, and color palette (AS and DS)
/ROPR: Raster command access (AS only)
NWS-1510/1530/1580
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