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There are four types of timing with which the /ACK signal is returned to the host.
1) Control port: When the wait signal is high (320 nsec)
2) Raster command (write): When /FIFL is high
3) Raster command (read): When /FIFL and /ROP are both high (This controller assumes
that the address data is fixed from the point at which /ACK
goes low to when /FIFL goes low.)
/Freq goes low if /FIFL id high (FIFO is empty) and /ROPDS is low (access from the
host). It remains low while /FIFL is low.
/FIFL is the signal that indicates that data is in FIFO. It goes low at the next
clock (F) after Freq becomes O. After the regis - ter is set (QE is high), it goes
high. This indicates that FIFO is empty.
One raster command can be loaded into FIFO. A raster command consists of data (DO -
DlS) and an address (Al - A16).
Fig. 4 is a timing chart.(page 3-61)
3-9-8. Rop registers
Execution of the command in FIFO begins when /Bust goes high.
Command execution is in two stages: register setting and FB
read/write. FB read/writes only takes place if A14 of the command address portion is
1. Register setting is based on the preceding QA. Registers set using commands are
as follows:
QA
L->H:
H:
H->L:
Register
Rop Mode Register(/SCOMR)
Source Rectangle X, Y Address (SSOUR, /SSOUR)
Destination Rec tang I e X, Y Address (SDEST, /SDEST)
Limit X Address(SLIMIT)
Rop Mask(/SROPM)
Data Register(/SDREG)
Source X, Y Address (/SSOUR)
Limit Y-Counter(/SLIMIT)
Destination X, Y Address(/SDEST)
Rop Function(SROPFOl-67)
Right/Left Mask Register(SDEST, SLIMIT)
Shift Counter(XSSC)
Dot Mask Register(XSDWR)
Read Plane Register
The req flag is set when QB is high and CA14 is 1.
It directs the rop mode
controller to perform a memory read/write.
HDREAD is the signal for outputting to the DH bus (HDO - 15),not data from the host
but rather data from the raster chip's ROM. It is active during read requests from
the host and when copies between planes are being executed.
The /psOl signal is for reading to the raster chip. It permits reading of the data
corresponding to the read plane reg. setting.
It is active when HDREAD is active and the source is not ROM.
3-9-9. Raster operation cycle controller (ROCC)
This controls rop execution (raster chip, address register, and memory) based on
commands from the host (when CA14 is high).
3-48
NWS-1510/1530/1580
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