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/GENEN:
/RAEN:
/SELORl, 2
/SELG:
address; 1:
Signal for enabling HD12 - 15. (input)
Signal for enabling RAO - 18. (input)
Switches data output on top of RAO - 18. 0: Destination
Source address (input)
XINC:
X address increase/decrease direction (input)
XLASTIN:
XELM, XELR control signal. (input)
/PRERM, /CLRERM
/NWR:
Control signal input to ROCC
0 when XINC=l and DRXA[ 0 - 3] - SRAX[ 0 - 3]
<
LXA[ 0 - 3]; 0 when XINC=O
and DRXA[0-3] -
SRAX[0-3]
>
LXA[0-3]; 1 otherwise. (output)
/PRD:
Control signal input
to
ROCC
0 when XINC=l and DRXA[ 0 - 3]
SRAX[ 0 - 3] < LXA[ 0 - 3]; 0 when XINC=O
and DRXA[ 0 - 3] -
SRAX[ 0 - 3] > LXA[ 0 - 3]; 0 when XINC=l and DRXA[ 0 -
3]
<
SRAX [ 0 - 3 ] ; 0 when XINC=O and DRXA [ 0 - 3 ]
>
SRAX [ 0 - 3 ] ; 1 other -
wise. (output)
/CLRDEST: Signal to clear destination X address [ 0 - 3].
/SFH:
Signal to clear source X address [ 0 - 3] .
(2) Control timing
CA12 - 1 and HD15 -
4
are used to set the address registers. There - fore they are
valid after commands written from the host are input to FIFO until the next input is
received. (They must be maintained at least when QA goes from low to high and while
QA is high and when QA goes from high to low.) SSOUR, SDEST and SLIMIT are generated
by QA.
RA18 - 1 is maintained from when /SELORl, 2 and /SELG change to when the address
increases or decreases
(ADCK), or until a new value is set by the host (SSOUR,
SDEST).
In order to make the timing of ADCK,
SSOUR and SDEST easier,
LS373 is
latched when fc is high. Therefore ADCK, SSOUR and SDEST can occur anytime when fc
is low.
The latched output becomes MA15 - 0 and a FB address. (If only DRAM were used, it
could be maintained by the /ras and
leas
trailing edges only, but since ROM is used
too, it is latched.
WPB3 - 0 (HD15 - 12 of uPD65013G) is a data signal from the rop chip's mask, shift and
rop func register. It must be maintained by the trailing edge of QA (SROPF, XSLM,
XSRM, XSSC). (When WPB3 - 0 sets the raster chip shift count, the value set at the
leading edge of QA (DRXA[ 0 - 3]
-
SRXA[ 0 - 3]) is used. Therefore, QA must last a
minimum of 60 nsec) This data is used by /SROPF, XSLM, XERM, XSSC and XSDWR.
XELM and XERM must be maintained when a mask is set in the FB (write per bit is
used, so maintenance is necessary for 35 nsec after the /ras trailing edge).
/NWR and /PRD are used by ROCC, so they must be maintained while
/NCK is low.
However, they change when an address is set by the host or due to XINC in the rop
mode, so it is sufficient if there is a period of 70 nsec between the SSOUR, SDEST,
and SLIMIT leading edges and the /NCK leading edge.
NWS-1510/1530/1580
3-55
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