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3-7. KEYBOARD/MOUSE
3-7-1.
Data Reception
The keyboard/mouse data receiving port is implemented using
circuit built into WSC-PARK.
Data is received as serial
input at 9600 bps from the keyboard and 1200 bps from the
mouse.
It is then converted into parallel form and
interrupts are issued to the CPU to indicate that data has
been received.
A 2-byte FIFO is built into PARK allowing 2
bytes of data to be stored.
An interrupt is generated when one byte has been received.
The interrupt is normally cleared after the CPU reads the
data, but if the second data byte has already been received,
the interrupt is not cleared.
The system is illustrated
below.
CN2
,.
KRXD
.
MRXD
RXD
:
KBDRXD
t----•
MOUSERXD - - - -
PARK
CPU
CDECR
FIFO #1
FIFO #2
-
SERIALto
~ o~ o~
PARALLEL
L--,/
L--,/
L--,/
The first byte of data immediately passes FIFO#l and is
latched to FIF0#2.
At this point an interrupt is generated.
The interrupt is cleared if the CPU immediately reads the
contents of FIF0#2.
If, before the CPU reads FIF0#2, the next data byte has
entered FIFO#l, the interrupt is not cleared even when the
CPU reads FIF0#2.
It is cleared only after the CPU reads the
3-36
NWS-1510/1530/1580
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