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b) LANCE-Buff er access by the CPU
<CPU>
LANCE-Buffer address output
R/W =output
FCO - 2 output
SIZO, 1 = output
AS= OS= "L"
<MEMC>
~------<-
PORT output
< CDECR >
IOSEL output
<PARK>
<
WSC - LANCE
>
~-----
ETHER output
Bus arbitration/
~------
Buffer enabled/
LCSX, etc. output
<Buffer>
Data read/ write
._
_ -
-
- - -- --
-
-
-
-
-
-
- -
-
- - -
- -
- - -
-
- - - - - -
- -
- - - -
-
- -
-
- - - - -
- -
- -
-
- - -
- -
-
- -
- - - - -
- -
- -
-
-
-
- - -
-
-
- - -
--
- -
-
- -
--
-
- -
-
- - _
_...
DSACKB output
DSACK1
AS= OS= "H"
' - - - - - - - - - - 1 -
PORT negated
1 - - - - - - - - - - -
ETHER negated
~-----.-i
IOSEL negated
~------.
DSACKB negated
End of cycle
3-3-7.
SCSI Access
It is possiole for the CPU to access the SCSI controller chip
(CXD1180) using the I/O bus while DMAC is executing data
transfers between SCSI and memory as shown below.
NWS-1510/1530/1580
3-15
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