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<CPU>
Interrupt received
FC
* -
"111"
A 1 - 3 =interrupt level
AS= "L"
AVEC received
AS= "H"
End of cycle
Service routine
initiated
< CDECR >
Interrupt received
IPLO - 2 encode output
<MEMC>
IACK output
IACK negated
3-5. CACHE BURST TRANSFER FUNCTION
<PARK>
AVEC output
AVEC negated
Interrupt cause
generation
SCCINT
=
"H"
The a command/data cache is built into the MC68030, the CPU
used by the PWS-1500 Series.
Its performance level is high,
but in order to speed up operation further using the cache,
a burst transfer function is provided for loading commands
and data.
Details are provided in the "MC68030 User's Manual"
provided by Motorola.
Here we provide only a brief
description of the operation of the hardware used for
implementing this function.
When the CPU is operating with the cache and it determines
that the commands or data to be executed next is not present
in the cache, it loads the necessary commands or data into
the cache from external memory.
The special type of cycle
3-30
NWS-1510/1530/1580
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