Chipset Features Setup - JETWAY J-Mark J-530CF Manual

3-3 CHIPSET FEATURES SETUP

This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
Auto Configuration
Refresh Rate Control
Ref/Act Command Delay
Refresh Queue Depth
RAS Precharge Time
RAS to CAS Delay
ISA Bus clock Frequency
Starting Point of Paging
NA# Enable
L2 Cache Burst RD Cycle
Asyn/Sync Mode CPU/DRAM : Asynchronous
SDRAM CAS Latency
SDRAM WR Retire Rate
DRAM Opt RAS Precharge
PCI Peer Concurrency
Read Prefetch Memory
Assert TRDY After Prefet
CPU to PCI Burst Mem. WR
CPU to PCI Post Write
Linear Mode SRAM Support
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
DRAM Settings: The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully chosen and should
only be altered if data is being lost. Such a scenario might well occur if your system had
mixed speed DRAM chips installed so that greater delays may be required to preserve
the integrity of the data held in the slower memory chips.
ROM PCI/ISA BIOS (2A5IMJ1A)
CHIPSET FEATURES SETUP
AWARD SOFTWARE ,INC
: Enabled ECC Function Support
: 15.6us AGP Aperture Size
: 6T System BIOS Cacheable
: 12 Video BIOS Cacheable
: 3T Memory Hole at 15M-16M
: 3T DRAM Controller 1 T WR
: PCICLK/4 DRAM Controller 1 T RD
: 1T PCI Post Write Buffer
: Enabled PCI Delayed Transaction : Disabled
: Delay 1T Auto Detect DIMM/PCI Clk : Enabled
Spread Spectrum
: 3T
: X-1-1-1
: Enabled
: Enabled
: Enabled Esc: Quit
: 2 QWs F1 : Help
: Enabled F5 : Old Values
: Enabled F6 : Load BIOS Defaults
: Disabled F7 : Load Setup Defaults
Figure 3-4
21
: Enabled
: 64MB
: Enabled
: Enabled
: Disabled
: Enabled
: Enabled
: Enabled
: Disabled
↑↓→←: Select Item
Pu/Pd/+/-:Modify
(Shift)F2 : Color