Spi Routing Guidelines; Figure 12-2. Spi Connections; Figure 12-3. Basic Spi Initiator And Target Connections; Figure 12-4. Spi Topologies - Nvidia Jetson Orin NX Series Product Manual

Figure 12-2. SPI Connections
SoC – SPI
GP47_SPI1_SCK
GP48_SPI1_MISO
GP49_SPI1_MOSI
GP50_SPI1_CS0
GP51_SPI1_CS1
GP36_SPI3_SCK
GP37_SPI3_MISO
GP38_SPI3_MOSI
GP39_SPI3_CS0
GP40_SPI3_CS1
Figure 12-3. Basic SPI Initiator and Target Connections
Jetson Initiator
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
12.2.1

SPI Routing Guidelines

The following guidelines meet the SPI routing guidelines.
Figure 12-4. SPI Topologies
Point-Point Topology
Jetson
SPI
SoC
Device
Main trunk
Table 12-5. SPI Interface Signal Routing Requirements
Parameter
Max frequency
Configuration / device organization
Max loading (total of all loads)
Reference plane
Breakout region impedance
Max PCB breakout delay
Trace impedance
Via proximity (signal to reference)
Trace spacing: Microstrip / Stripline
Max trace length/delay (PCB main trunk) For MOSI, MISO, SCK and CS
Point-point
2x-load star/daisy
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series
SPI0_SCK
91
SPI0_MISO
93
SPI0_MOSI
89
SPI0_CS0*
95
SPI0_CS1*
97
SPI1_SCK
106
SPI_MISO
108
SPI1_MOSI
104
SPI1_CS0*
110
SPI1_CS1*
112
SPI Target
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
2x-Load Star Topology
Jetson
Branch-A
SoC
Main trunk
Branch-B
Connect to up to 2 SPI
devices (separate CS
for each)
Connect to up to 2 SPI
devices (separate CS
for each)
Jetson Target
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
SPI
Device
#1
Jetson
SPI
SoC
Device
#2
Requirement
65
4
15
GND
Minimum width
and spacing
75
50 60
< 3.8 (24) mm (ps)
4x / 3x dielectric
195 (1228) mm (ps)
120 (756)
DG-10931-001_v1.1 | 70
Miscellaneous Interfaces
SPI Initiator
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
2x-Load Daisy Topology
SPI
Device
Branch-A #1
Main trunk Branch-B
Units Notes
MHz
load
pF
ps
±15%
See Note
SPI
Device
#2