Table 7-3. Uphy0 Mapping Options (Usb 3.2 And Pcie); Table 7-4. Uphy2 Mapping Options (Pcie) - Nvidia Jetson Orin NX Series Product Manual

Pin Module Pin Orin SoC Pin Name
# Name (See Note 4)
HS_UPHY0_L2_RX_
51 DP0_TXD2_N
N
53 DP0_TXD2_P HS_UPHY0_L2_RX_P
57 DP0_TXD3_N HS_UPHY0_L2_TX_N
59 DP0_TXD3_P HS_UPHY0_L2_TX_P
Notes:
1. In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals.
2. The direction shown in this table for GPxxx_PCIEx_RST* and GP185_PCIE_WAKE* signals is true when used for those PCIe
functions. Otherwise, if used as GPIOs, the direction is bidirectional.
3. The light blue highlighting for some of the module pins/functions is just to highlight the different functionality on those pins.
4. The table above shows Module Pin Names and Orin SoC Pin Names. For the Orin Module Function, which can be very different
than the Module Pin name, see the Pinout Matrix, full Pin Desc. xls attached to this document, or Table 7-3 below.
The following tables shows the supported UPHY mapping for the UPHY blocks [2,0]. The
mapping tables indicate which lanes of each UPHY block can be assigned for USB or PCIe.
Only one of the supported configurations per UPHY block can be used in a design. Each UPHY
block is programmed independently. It is not required to select the same configuration on
both UPHY blocks.
Table 7-3. UPHY0 Mapping Options (USB 3.2 and PCIe)
Orin Module Pin Orin Module
Names Functions
PCIE0_RX0/TX0 PCIe #0 Lane 0
PCIE0_RX1/TX1 PCIe #0 Lane 1
PCIE0_RX2/TX2 PCIe #0 Lane 2
PCIE0_RX3/TX3 PCIe #0 Lane 3
PCIE1_RX0/TX0 PCIe #1 Lane 0
USBSS_RX/TX USB 3.2 #1
DP0_TXD[1:0]_N/P USB 3.2 #2
DP0_TXD[3:2]_N/P USB 3.2 #3
Table 7-4. UPHY2 Mapping Options (PCIe)
Orin Module Pin
Names
CSI4_D[0:2]_RX0/TX0
CSI4_D[1:3]_RX1/TX1
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series
Usage and Description
USB 3.2 Receive (Port #2)
USB 3.2 Transmit (Port #2)
UPHY0 Lanes
UPHY0, Lane 4
UPHY0, Lane 5
UPHY0, Lane 6
UPHY0, Lane 7
UPHY0, Lane 3
UPHY0, Lane 0
UPHY0, Lane 1
UPHY0, Lane 2
Orin Module
Functions UPHY2 Lanes
PCIe #2 Lane 0 Lane 0
PCIe #2 Lane 1 Lane 1
Recommended
Usage
USB 3.2
connector,
device or hub
Orin Module Configurations
Option #1 Option #2
PCIe x4 (C4), RP PCIe x4 (C4), EP
PCIe x1 (C1), RP PCIe x1 (C1), RP
Limited to Gen2
USB 3.2 (P0) USB 3.2 (P0)
USB 3.2 (P1) USB 3.2 (P1)
USB 3.2 (P2) USB 3.2 (P2)
Orin Module Configurations
Option #1
PCIe x2 (C7), RP
USB and PCIe
Pin
Direction Type
USB 3.2
Input
PHY
USB 3.2
Output
PHY
Option #3
PCIe x4 (C4), EP
PCIe x1 (C1), RP
USB 3.2 (P0)
USB 3.2 (P1)
Unused
Option #2
PCIe x1 (C7), RP
PCIe x1 (C9), RP
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