Table 7-2. Jetson Orin Module Usb 3.2 And Pcie Pin Description - Nvidia Jetson Orin NX Series Product Manual

Table 7-2. Jetson Orin Module USB 3.2 and PCIe Pin Description
Pin Module Pin Orin SoC Pin Name
# Name (See Note 4)
HS_UPHY0_L4_RX_
131 PCIE0_RX0_N
N
133 PCIE0_RX0_P HS_UPHY0_L4_RX_P
HS_UPHY0_L5_RX_
137 PCIE0_RX1_N
N
139 PCIE0_RX1_P HS_UPHY0_L5_RX_P
HS_UPHY0_L6_RX_
149 PCIE0_RX2_N
N
151 PCIE0_RX2_P HS_UPHY0_L6_RX_P
HS_UPHY0_L7_RX_
155 PCIE0_RX3_N
N
157 PCIE0_RX3_P HS_UPHY0_L7_RX_P
134 PCIE0_TX0_N HS_UPHY0_L4_TX_N
136 PCIE0_TX0_P HS_UPHY0_L4_TX_P
140 PCIE0_TX1_N HS_UPHY0_L5_TX_N
142 PCIE0_TX1_P HS_UPHY0_L5_TX_P
148 PCIE0_TX2_N HS_UPHY0_L6_TX_N
150 PCIE0_TX2_P HS_UPHY0_L6_TX_P
154 PCIE0_TX3_N HS_UPHY0_L7_TX_N
156 PCIE0_TX3_P HS_UPHY0_L7_TX_P
GP184_PCIE4_RST_
181 PCIE0_RST*
N
GP183_PCIE4_
180 PCIE0_CLKREQ*
CLKREQ_N
SF_PCIE4_CLK_N
160 PCIE0_CLK_N HS_UPHY0_
REFCLK2_N
SF_PCIE4_CLK_P
162 PCIE0_CLK_P HS_UPHY0_
REFCLK2_P
HS_UPHY0_L3_RX_
167 PCIE1_RX0_N
N
169 PCIE1_RX0_P HS_UPHY0_L3_RX_P
172 PCIE1_TX0_N HS_UPHY0_L3_TX_N
174 PCIE1_TX0_P HS_UPHY0_L3_TX_P
GP178_PCIE1_RST_
183 PCIE1_RST*
N
GP177_PCIE1_
182 PCIE1_CLKREQ*
CLKREQ_N
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series
Usage and Description
PCIe #0 Receive 0 (PCIe Ctrl #4 Lane 0)
PCIe #0 Receive 1 (PCIe Ctrl #4 Lane 1)
PCIe #0 Receive 2 (PCIe Ctrl #4 Lane 2)
PCIe #0 Receive 3 (PCIe Ctrl #4 Lane 3)
PCIe #0 Transmit 0 (PCIe Ctrl #4 Lane 0)
PCIe #0 Transmit 1 PCIe Ctrl #4 Lane 1)
PCIe #0 Transmit 2 (PCIe Ctrl #4 Lane 2)
PCIe #0 Transmit 3 (PCIe Ctrl #4 Lane 3)
to 3.3V on the module. Output when module
is Root Port or input when module is
Endpoint.
PCIE #0 Clock Request (PCIe Ctrl #4).
-up to 3.3V on the Orin module.
Input when Orin module is Root Port or
output when Orin module is Endpoint.
PCIe #0 Reference Clock controlled by on-
module mux by SoC GP21. When GP21 is
low, SF_PCIE4_CLK is selected (reference
clock when Orin module is Root Port). When
GP21 is high, UPHY0_REFCLK2_IN is
selected (reference clock input when Orin
module is an Endpoint).
PCIe #1 Receive 0 (PCIe Ctrl #1 Lane 0)
PCIe #1 Transmit 0 (PCIe Ctrl #1 Lane 0)
to 3.3V on the module.
PCIE #1 Clock Request (PCIe Ctrl #1).
-up to 3.3V on the module.
USB and PCIe
Recommended
Usage Direction
Input
PCIe x4
Output
conn/device (i.e.
M.2 Key M)
-up
Bidir
Bidir
Input
PCIe x1
Output
conn/device (i.e.
M.2 Key E)
-up
Output
Bidir
DG-10931-001_v1.1 | 27
Pin
Type
PCIe PHY
PCIe PHY
Open
Drain 3.3V
PCIe PHY
PCIe PHY
PCIe PHY
Open
Drain 3.3V
Open
Drain 3.3V