Hdmi; Figure 9-6. Hdmi Connection Example - Nvidia Jetson Orin NX Series Product Manual

9.2

HDMI

A standard DP 1.4 or HDMI v2.1 interface is supported. See Figure 9-6 for more details.
Figure 9-6. HDMI Connection Example
Jetson
SoC – DP/HDMI
GP74_HPD0_N
SF_DPAUX01_N
SF_DPAUX01_P
GP05_HDMI_CEC
HS_DISP0_HDMI_CK_DP3_P
HS_DISP0_HDMI_CK_DP3_N
HS_DISP0_HDMI_D0_DP2_P
HS_DISP0_HDMI_D0_DP2_N
HS_DISP0_HDMI_D1_DP1_P
HS_DISP0_HDMI_D1_DP1_N
HS_DISP0_HDMI_D2_DP0_P
HS_DISP0_HDMI_D2_DP0_N
Load Switch
VDD_3V3_SYS
IN
MOD_SLEEP*
EN
100kΩ
Notes:
1. Level shifters required on DDC/HPD. NVIDIA Orin pads are not 5V tolerant and cannot
directly meet HDMI VIL/VIH requirements. HPD level shifter can be non-inverting or
inverting. The HPD level shifter in the reference design is inverting. The reference design
uses a BJT level shifter, and a resistor divider is needed. See the reference design if a
similar approach will be used.
2. If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal
quality, which must meet the timing and electrical requirements of the HDMI specification
for the modes to be supported. See requirements and recommendations in the related
3. The DP1_TXx pads are native DP pads and require series AC capacitors (ACCAP) and pull-
module is off or in sleep mode to meet the HDMI VOFF requirement. The enable to the FET,
enables the pull-downs when the HDMI interface is to be used. Chokes between pull-downs
and FET are optional improvements for HDMI 2.0 operation.
4. See the RS section in Table 9-5 for details.
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series
VDD_5V_SYS
VDD_1V8
DP1_HPD
96
S
DP1_AUX_N
98
DP1_AUX_P
100
HDMI_CEC
94
0.1uF
DP1_TXD3_N
81
0.1uF
DP1_TXD3_P
83
0.1uF
DP1_TXD2_N
75
0.1uF
DP1_TXD2_P
77
0.1uF
DP1_TXD1_N
69
0.1uF
DP1_TXD1_P
71
0.1uF
DP1_TXD0_N
63
0.1uF
DP1_TXD0_P
65
VDD_3V3_HDMI
OUT
10kΩ
VDD_5V0_HDMI_CON
Load Switch
IN OUT
EN
VDD_3V3_HDMI
0.1uF
D
G G
S
D D
S
VDD_3V3_SYS
G
D
S
TPD4E 02B04 DQO R
-downs must be disabled when Orin
100kΩ
G
100kΩ
Type A
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
RESERVED
CEC
R
CK–
S
R
CK_SHIELD
S
CK+
R
D0–
S
R
D0_SHIELD
S
D0+
R
D1–
S
R
D1_SHIELD
S
D1+
R
D2–
S
R
D2_SHIELD
S
D2+
See
Note 4
Table 9-5).
DG-10931-001_v1.1 | 52
Display
HDMI
19
18
17
16
15
14
13
12
11
10
9
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5
4
3
2
1