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Nvidia Jetson Orin NX Series Product Manual

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Jetson Orin NX Series and Jetson Orin
Nano Series
Product Design Guide
DG-10931-001_v1.1
|
April 2023
PRELIMINARY INFORMATION SUBJECT TO CHANGE

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Summary of Contents for Nvidia Jetson Orin NX Series

  • Page 1 Jetson Orin NX Series and Jetson Orin Nano Series Product Design Guide DG-10931-001_v1.1 April 2023 PRELIMINARY INFORMATION SUBJECT TO CHANGE...
  • Page 2 Figure 9-1: Corrected P/N swap for SoC DPAUX pins • Figure 9-2: Corrected P/N swap for SoC DPAUX and PIAUX221Z • device. Figure 9-8: Corrected P/N swap for SoC DPAUX • PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | ii...
  • Page 3 Added pulldown and series resistors on HPD after level shifter. > Added details of HDMI_CEC circuit & HPD/DDC level shifters. Figure 10-1 and Figure 10-2: Separated 2-lane and 4-lane • configuration option examples. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | iii...
  • Page 4 Table 12-1 and Figure 12-1: Added I2C usage on the module for I2C0 • and I2C2. • Table 13-2: Updated pull-up voltage and/or pull-up resistor values for several pins. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | iv...

  • Page 5: Table Of Contents

    Common USB Routing Guidelines ..............34 PCIe ........................... 36 7.2.1 PCIe Routing Guidelines .................... 38 Chapter 8. Gigabit Ethernet ................... 43 8.1.1 Ethernet MDI Routing Guidelines................44 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | v...
  • Page 6 17.4 Routing Guidelines ......................82 17.4.1 General PCB Routing Guidelines ................83 17.5 Common High-Speed Interface Requirements .............. 84 17.6 Test Points for High-Speed Interfaces ................85 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | vi...
  • Page 7 Chapter 18. USB 3.2 and Wireless Coexistence............86 18.1 Mitigation Techniques ...................... 86 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | vii...
  • Page 8 Figure 10-2. CSI 4-Lane Connection Options................61 Figure 10-3. Available Camera Control Pins ................61 Figure 11-1. Audio Connection Example .................. 65 Figure 12-1. I2C Connections....................68 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | viii...
  • Page 9 Figure 12-8. Debug UART Connections ..................75 Figure 17-1. General PCB Routing Guidelines ................ 83 Figure 17-2. Common Mode Choke ..................84 Figure 17-3. Serpentine ......................85 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | ix...
  • Page 10 Miscellaneous Camera Connections ..............63 Table 11-1. Orin Module Audio Pin Descriptions ..............64 Table 11-2. I2S Interface Signal Routing Requirements ............65 Table 11-3. Audio Signal Connection ..................66 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | x...
  • Page 11 Pins with External Pull-Ups to Supply on before SYS_RESET* Inactive ... 77 Table 14-1. Unused MPIO Pins and Pin Group ............... 78 Table 17-1. Signal Type Codes ....................81 Table 17-2. Common High-Speed Interface Requirements ..........84 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | xi...

  • Page 12: Chapter 1. Introduction

    Jetson Orin NX and Jetson Orin Nano Series Pinmux  Jetson Orin NX Series and Jetson Orin Nano Series Thermal Design Guide  Jetson Orin NX Series and Jetson Orin Nano Series SCL (Supported Component List)  PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series...

  • Page 13: Attachments

    Inter IC Sound Interface Low Dropout (voltage regulator) LPDDR5 Low Power Double Data Rate DRAM, Fifth generation Medium-Dependent Interface MIPI Mobile Industry Processor Interface Millimeter Milliseconds PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 2...
  • Page 14 8P8C modular connector used in Ethernet and other data links Real Time Clock Single-Ended System on Chip System on Module Serial Peripheral Interface TMDS Transition-Minimized Differential Signaling UART Universal Asynchronous Receiver-Transmitter Universal Serial Bus PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 3...

  • Page 15: Chapter 2. Jetson Orin Module

    DP_AUX/HPD, CEC Debug UART I2S interface (2x) System Power control, reset, alerts Audio Main input and pin for optional battery Codec clock Power back-up for Real-Time Clock PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 4...

  • Page 16: Figure 2-1. Jetson Orin Module Block Diagram

    CSI2_CLK_N CSI2_CLK_N CSI3_CLK_P CSI3_CLK_P CSI2_CLK_P CSI2_CLK_P CSI3_D1_N CSI3_D1_N CSI2_D1_N CSI2_D1_N CSI3_D1_P CSI3_D1_P CSI2_D1_P CSI2_D1_P DP0_TXD0_N USBSS1_RX_N CSI4_D2_N PCIE2_RX0_N DP0_TXD0_P USBSS1_RX_P CSI4_D2_P PCIE2_RX0_P DP0_TXD1_N USBSS1_TX_N CSI4_D0_N PCIE2_TX0_N PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 5...
  • Page 17 GPIO03 GPIO03 GPIO04 GPIO04 GPIO05 GPIO05 GPIO06 GPIO06 PCIE0_RX0_N PCIE0_RX0_N PCIE0_RX0_P PCIE0_RX0_P PCIE0_TX0_N PCIE0_TX0_N PCIE0_TX0_P PCIE0_TX0_P PCIE0_RX1_N PCIE0_RX1_N PCIE0_RX1_P PCIE0_RX1_P PCIE0_TX1_N PCIE0_TX1_N PCIE0_TX1_P PCIE0_TX1_P CAN_RX CAN_RX PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 6...
  • Page 18 SDMMC_CMD PCIE3_CLK_N GPIO13 GPIO13 SDMMC_CLK PCIE3_CLK_P GPIO14 GPIO14 I2C2_SCL I2C2_SCL SHUTDOWN_REQ* SHUTDOWN_REQ* I2C2_SDA I2C2_SDA PMIC_BBAT PMIC_BBAT UART2_TXD UART2_TXD POWER_EN POWER_EN UART2_RXD UART2_RXD SYS_RESET* SYS_RESET* SLEEP/WAKE* SLEEP/WAKE* PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 7...
  • Page 19 Jetson Orin Module Function Function VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN VDD_IN Legend Ground Power Function Significantly Different than Module Pin Name Implies PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 8...

  • Page 20: Chapter 3. Jetson Orin Module Boot Considerations

    SYS_RESET* system is powered on. is the SoC RCM0 strap Only supports USB FORCE_RECOVERY* USB0_D_N/P Recovery Mode PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 9...
  • Page 21 Jetson Orin module will configure USB0 as a device and enter recovery mode. See the USB section (Section 0) for an example figure that shows USB0 connected to a USB Micro B connector. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 10...

  • Page 22: Chapter 4. Developer Kit Feature Considerations

    NVIDIA Jetson Orin Nano Developer Kit carrier board if desired. In addition, aspects of the design that are specific to the NVIDIA developer kit usage but not useful or supported on a custom carrier board are also identified.

  • Page 23: Usb Superspeed Hub

    The reference design features that should not be copied as they are not required or useful for a custom carrier board design. The ID EEPROM (U17) is a feature that is used for NVIDIA internal purposes, but not recommended on a custom design. If a similar functionality is terface.

  • Page 24: Chapter 5. Modular Connector

    Other SODIMM connector heights are available. If a different height connector is used, the standoff height will have to be adjusted accordingly to account for the difference in height from main PCB to module PCB. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 13...

  • Page 25: Module Installation And Removal

    Secure the module to the baseboard with screws into the standoff or spacer (shown in Figure 5-2). Figure 5-2. Module to Connector Assembly Diagram Mounting Screw Standoff To remove the module correctly, follow the installation sequence in reverse. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 14...

  • Page 26: Chapter 6. Power

    Signal for module on/off: high level on, low level System Input Analog off. Connects to module Power Sequencer / 5.0V PMIC power on/off control input through converter logic. POWER_EN is routed to a PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 15...

  • Page 27: Power Supply And Sequencing

    The buffers should only be enabled towards the module when SYS_RESET* goes high. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 16...
  • Page 28 ID level to be high if an advanced module is installed. The module ID pin level should be used on the carrier board to determine if only 5V is supplied to (legacy module) or VDD_IN the full advanced module range. VDD_IN PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 17...

  • Page 29: Figure 6-1. System Power And Control Block Diagram

    2. Designs which implement an eFUSE or current limiting device on the input power rail of the module should select a part that DOES NOT limit reverse current. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 18...

  • Page 30: Figure 6-3. Power Up Sequence No Power Button Auto Power On

    2. SYS_RESET* is driven by the Power Sequencer or PMIC during power up. Note: For designs that intend to follow the NVIDIA carrier board design and include the EFM8SB10F2G-A-QFN20 MPU for Power Button control, see 6.1.1 Power Button Supervisor MCU Power-On.

  • Page 31: Figure 6-5. Power Down Initiated By Shutdown_Req* Assertion

    T > 10mS Note: SHUTDOWN_REQ* must always be serviced by the carrier board to toggle POWER_EN from high to low, even in cases of sudden power loss. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 20...

  • Page 32: Power Button Supervisor Mcu Power-On

    ON/OFF signals to the system. The selected MCU to perform this function is the EFM8SB10F2G-A-QFN20 from Silicon Labs. Note: Designs that intend to follow the NVIDIA carrier board design and include the EFM8SB10F2G-A-QFN20 MPU for Power Button control need to replicate the circuitry on the latest P3768 carrier board exactly.

  • Page 33: Figure 6-7. Power-On Button Circuit

    Note: Button initiated power on is enabled if the ACOK line is pulled to GND (J1 in figure installed). Auto-Power-On is enabled if the ACOK line is not pulled to GND (J1 not installed - circuit drives ACOK high). PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 22...

  • Page 34: Defined Behaviors

    Parameter Typical Units T_PB_DET SLEEP/WAKE* (power button) detect (de-bounce only) T_VPWR_ON Delay from power button active to POWER_EN T_PE_RST SYS_RESET* inactive delay from POWER_EN rising edge PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 23...

  • Page 35: Power-Off -> Power-On (Auto-Power-On Case)

    For the long button press case, system is forced to shut down at about the 10 second mark without software involvement. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 24...

  • Page 36: Figure 6-10. Power-On To Off Power Button Held Low > 10 Seconds

    Parameter Typical Units T_ON Power button active duration for forced OFF > 10 (T_PWR_ON + T_MPO_ON + T_CPO + T_MPO_OFF1) T_PWR_OFF Delay to first rail OFF PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 25...

  • Page 37: Chapter 7. Usb And Pcie

    (i.e. M.2 Key E) USB2_D_P HS_USB0_P2_P Note: In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 26...

  • Page 38: Table 7-2. Jetson Orin Module Usb 3.2 And Pcie Pin Description

    3.3V on the module. Drain 3.3V GP177_PCIE1_ PCIE #1 Clock Request (PCIe Ctrl #1). Open PCIE1_CLKREQ* Bidir CLKREQ_N -up to 3.3V on the module. Drain 3.3V PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 27...
  • Page 39 USB 3.2 Receive (Port #1) Input USB 3.2 DP0_TXD0_P HS_UPHY0_L1_RX_P connector, device or hub DP0_TXD1_N HS_UPHY0_L1_TX_N USB 3.2 USB 3.2 Transmit (Port #1) Output DP0_TXD1_P HS_UPHY0_L1_TX_P PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 28...

  • Page 40: Table 7-3. Uphy0 Mapping Options (Usb 3.2 And Pcie)

    CSI4_D[0:2]_RX0/TX0 PCIe #2 Lane 0 Lane 0 PCIe x2 (C7), RP PCIe x1 (C7), RP CSI4_D[1:3]_RX1/TX1 PCIe #2 Lane 1 Lane 1 PCIe x1 (C9), RP PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 29...

  • Page 41: Usb

    1. AC capacitors should be located close to either the USB connector, or the Orin module pins. 2. Connector used must be USB Implementers Forum certified if USB 3.2 is implemented. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 30...

  • Page 42: Usb 2.0 Routing Guidelines

    > 8 budget [*] the consideration of Gen1 fixture loss Time-domain Reflectometer (TDR) Dip @ Tr = 200ps (10%-90%) Gen1 @ Tr = 61ps (10%-90%) Gen2 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 31...
  • Page 43 Place GND via as symmetrically as GND via is used to maintain return possible to data pair vias. Up to 4 path, while its Xtalk suppression is limited PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 32...
  • Page 44 SMT Connector GND Voiding GND plane under signal pad should be voided. Size of void should be the same size as the pad. Connector used must be USB-IF certified PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 33...

  • Page 45: Common Usb Routing Guidelines

    Keep critical USB related traces away from other signal traces or unrelated power traces and areas or power supply components. Table 7-7. Orin USB 2.0 Signal Connections Module Ball Name Type Termination Description PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 34...

  • Page 46: Table 7-8. Miscellaneous Usb 2.0 Signal Connections

    3.2 connectors, hubs, or DP0_TXD2_N/P (USB 3.2 Port #2) peripheral TX lines. ESD other devices on the PCB. protection near connector if required. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 35...

  • Page 47: Pcie

    PCIE2_RST* GP188_PCIE7_RST_N SDMMC_DAT3 PCIE3_CLKREQ* PCIe 3 (Ctrl #9) – GP191_PCIE9_CLKREQ_N SDMMC_DAT2 PCIE3_RST* GP192_PCIE9_RST_N PCIe x1) PCIE_WAKE* Shared wake pin GP185_PCIE_WAKE_N HS_UPHY0 _REFCLK2/ GP21 SF_PCIE4_CLK Mux Control PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 36...

  • Page 48: Figure 7-6. Pcie Endpoint Connections Example

    PCIe connector, M.2 Key M, etc. In those cases, the AC caps are on the board connected to those connectors. 3. See design guidelines for correct AC capacitor values. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 37...

  • Page 49: Pcie Routing Guidelines

    (See Note 1). EM-370(Z) PCB Routing to 2 Orin Module dB / mm (ps) material is assumed in the length/delay Insertion loss / length (delay) -14.74 / 248 (1587) calculations: PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 38...
  • Page 50 Remove unwanted GND fill that is either floating or act like antenna Connector Voiding Void all layers of golden finger area under the pad ~0.15mm larger than the pad size is recommended. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 39...

  • Page 51: Figure 7-7. Insertion Loss S-Parameter Plot Sdd21

    The max length and delay numbers are examples. These should be updated based on the actual PCB material loss and the loss for the end device and any additional connections. Figure 7-7. Insertion Loss S-Parameter Plot SDD21 Figure 7-8. Insertion Loss S-Parameter Plot SDD11 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 40...

  • Page 52: Table 7-11. Pcie Signal Connections

    TX_N/P pin of PCIe device through AC cap according CSI4_D2_N/P module pins or device to supported configuration. (PCIE2_RX0_N/P) if device on main PCB. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 41...
  • Page 53 This isolates the on- module pull-up resistors as well as ensures this signal will not be pulled or driven high before the Root Port is powered on. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 42...

  • Page 54: Chapter 8. Gigabit Ethernet

    Jetson 3.3V UPHY2 GP189_PCIE8_CLKREQ_N GP190_PCIE8_RST_N GBE_MDI0_P GBE_MDI0_N GP185_PCIE_WAKE_N GBE_MDI1_P HS_UPHY2_L3_TX_N GBE_MDI1_N HS_UPHY2_L3_TX_P GBE_MDI2_P GBE_MDI2_N To Magnetics/ HS_UPHY2_L3_RX_N GBE_MDI3_P RJ45 Connector HS_UPHY2_L3_RX_P GBE_MDI3_N SF_PCIE8_CLK_N GBE_LED_ACT SF_PCIE8_CLK_P GBE_LED_LINK PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 43...

  • Page 55: Ethernet Mdi Routing Guidelines

    Ideally there should be no vias, but if required for breakout to Ethernet controller or magnetics, keep very close to either device. Notes: NVIDIA Orin does not support delay or skewing of clock vs. data. This must be enabled in the PHY. Table 8-3. Ethernet Signal Connections...

  • Page 56: Chapter 9. Display

    A standard DP 1.4 or HDMI v2.0 interface is supported. These share the same set of interface pins. Therefore, either DisplayPort or HDMI can be supported natively. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 45...

  • Page 57: Edp And Dp

    The level shifter must be non-inverting (preserve the polarity of the HPD signal from the display). See the HPD level shifter detail block in the figure above. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 46...

  • Page 58: Edp And Dp Routing Guidelines

    The following routing requirements meet the eDP and DP routing guidelines. Figure 9-3. eDP and DP Differential Main Link Topology Jetson Common Mode Chokes & ESD Driver Conn PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 47...

  • Page 59: Table 9-3. Edp And Dp Main Link Signal Requirements Including Dp_Aux

    Max trace length (delay) from module to connector 6.9ps/mm assumption for Stripline, 5.9ps/mm for Microstrip. RBR/HBR Stripline 215 (1137.5) mm (ps) Microstrip 215 (975) HBR2 Stripline 184 (1260) Microstrip 178 (1050) HBR3 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 48...
  • Page 60 Not limited if total channel loss meets IL spec Max Via Stub Length AC Cap Value Discrete 0402 Max Dist. from AC cap to connector RBR/HBR No requirement HBR2/HBR3 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 49...

  • Page 61: Figure 9-4. S-Parameter Up To Hbr2

    The following figures show the eDP and DP interface signal routing requirements. Figure 9-4. S-Parameter Up to HBR2 PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 50...

  • Page 62: Figure 9-5. S-Parameter Up To Hbr3

    100k series resistor and 100k resistor to eDP/DP: Hot Plug Detect: Connect to HPD GND then Level shifter (non-inverting) pin on display connector through level shifter. between connector and module pin. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 51...

  • Page 63: Hdmi

    TPD4E 02B04 DQO R Notes: 1. Level shifters required on DDC/HPD. NVIDIA Orin pads are not 5V tolerant and cannot directly meet HDMI VIL/VIH requirements. HPD level shifter can be non-inverting or inverting. The HPD level shifter in the reference design is inverting. The reference design uses a BJT level shifter, and a resistor divider is needed.

  • Page 64: Hdmi Routing Guidelines

    IL/FEXT plot: See HDMI Guideline TDR plot: See Figure 9-9 Figure 9-8 Impedance Trace impedance: Diff pair breakout and main route is an implementation option. Reference plane Trace spacing/Length/Skew PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 53...
  • Page 65 GND via should be > 0.6mm Max # of vias PTH via 2 if all vias are PTH via u-via Not limited if total channel loss meets IL spec. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 54...
  • Page 66 Must be placed after AC cap Placement: Layer of placement Same layer as AC cap. The FET and choke can be placed on the opposite layer thru a PTH via PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 55...
  • Page 67 One 45° Trace between components Uncoupled structure HDMI connector Connector voiding Voiding the ground below the signal lanes 0.1448 (5.7 mil) larger than the pin itself PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 56...

  • Page 68: Figure 9-8. Il/Fext Plot

    Solutions with flex/2nd PCB may not achieve maximum frequency operation. The following figures show the HDMI interface signal routing requirements. Figure 9-8. IL/FEXT Plot Figure 9-9. TDR Plot PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 57...

  • Page 69: Table 9-6. Hdmi Signal Connections

    HDMI 5V supply to connector: Connect recommended) on supply near connector and ESD to +5V on HDMI connector. to GND. Note: Any ESD and/or EMI solutions must support targeted modes (frequencies). PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 58...

  • Page 70: Chapter 10. Mipi Csi Video Input

    Camera, CSI 3 Data 1 CSI3_D1_P HS_CSI3_D1_P Notes: In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 59...

  • Page 71: Figure 10-1. Csi 2-Lane Connection Options

    HS_CSI2_D1_P CSI3_CLK_N HS_CSI3_CLK_N CSI3_CLK_P HS_CSI3_CLK_P CSI3_D0_N Camera 4 HS_CSI3_D0_N CSI3_D0_P (2-Lane) HS_CSI3_D0_P CSI3_D1_N HS_CSI3_D1_N CSI3_D1_P HS_CSI3_D1_P Note: CSI_0_D1 and CSI_1_D0 have P/N swapped on the module. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 60...

  • Page 72: Figure 10-2. Csi 4-Lane Connection Options

    CAM_I2C_SDA GP55_I2C3_DAT CAM0_MCLK Camera 0 GP52_CLK1 CAM0_PWDN GP121_UART4_CTS_N Clock/Control CAM1_MCLK Camera 1 GP53_CLK2 CAM1_PWDN GP161_SPI5_CLK Clock/Control GPIO01 Camera 2 Clock GP65 GPIO11 GP66 Camera 3 Clock PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 61...

  • Page 73: Csi Routing Guidelines

    1 Gbps (Stripline/Microstrip) 2526 (421) / 2487 (421) ps (mm) 1.5 Gbps 1913 (319) / 1885 (319) 2.5 Gbps 900 (150) / 886 (150) Max intra-pair skew PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 62...

  • Page 74: Table 10-5. Mipi Csi Signal Connections

    Camera Initiator Clocks: Connect to camera reference clock inputs. GPIO01 (opt. MCLK2) GPIO11 (opt. MCLK3) CAM[1:0]_PWDN Camera Power Control signals (or GPIOs [1:0]): Connect to power down pins on camera(s). PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 63...

  • Page 75: Chapter 11. Audio

    Chapter 11. Audio NVIDIA Orin supports multiple PCM and I2S audio interfaces. It also includes a flexible audio port switching architecture. Table 11-1. Orin Module Audio Pin Descriptions Module Pin Recommended Pin # Orin Signal Usage/Description Direction Pin Type Name...

  • Page 76: I2S Routing Guidelines

    In (ps) Max trace length/delay skew between SCLK and ~1.6 (250) In (ps) SDATA_OUT/IN Note: Up to four signal vias can share a single GND return via. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 65...

  • Page 77: Table 11-3. Audio Signal Connection

    I2S Data Output: Connect to data input pin of audio device. I2S[1:0]_DIN I2S Data Input: Connect to data output pin of audio device. GPIO09 Audio Codec Initiator Clock: Connect to clock pin of audio codec. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 66...

  • Page 78: Chapter 12. Miscellaneous Interfaces

    EEPROM on the module with I2C address 7/h50. GP127_I2C1_DA I2C2_SDA Drain 1.8V Notes: In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 67...

  • Page 79: I2C Design Guidelines

    2. Avoid routing I2C signals near noisy traces, supplies or components such as a switching power regulator. 3. No requirement for decoupling caps for PWR reference. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 68...

  • Page 80: Spi

    SPI 1 Chip Select 1 SPI #1 Device #1 Notes: In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 69...

  • Page 81: Spi Routing Guidelines

    Trace spacing: Microstrip / Stripline 4x / 3x dielectric Max trace length/delay (PCB main trunk) For MOSI, MISO, SCK and CS Point-point 195 (1228) mm (ps) 2x-load star/daisy 120 (756) PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 70...

  • Page 82: Uart

    UART1_TXD. These have output-only buffers on the module to keep them from being affected by connected devices during boot as they are associated with SoC strapping pins. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 71...

  • Page 83: Can

    2. The direction indicated for the CAN signals are associated with that usage. The pins support GPIO functionality, so support b oth input and output operation (bidirectional). PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 72...

  • Page 84: Can Routing Guidelines

    GPIO. Orin (SoC) Technical Reference Manual (TRM)  Functional descriptions and related registers can be found in the TRM for the • FAN_PWM (PWM chapter). PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 73...

  • Page 85: Debug

    UART #2 Transmit: Connect to RX pin of serial device UART2_RXD If level shifter implemented, UART #2 Receive: Connect to TX pin of serial device -Orin module side of the device. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 74...

  • Page 86: Figure 12-8. Debug Uart Connections

    Note: If level shifter is implemented, pull-up is required on the RXD line on the non-Orin module side of the level shifter. This is required to keep the input from floating and toggling when no device is connected to the debug UART. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 75...

  • Page 87: Chapter 13. Pads

    FAN_TACH the signal edges. Care should be taken if the Schmitt-trigger mode setting is changed from the default initialization mode as this can influence interface timing. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 76...

  • Page 88: Pins Pulled Or Driven High During Power-On

    Orin Module Pin Pull-Up Supply External Orin Module Pin Pull-Up Supply External Voltage (V) Pull-U Voltage (V) Pull-U I2C0_SCL/SDA GPIO00 I2C1_SCL/SDA PCIE[3:0]_CLKREQ* I2C2_SCL/SDA PCIE[3:0]_RST* CAM_I2C_SCL/SDA PCIE_WAKE* PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 77...

  • Page 89: Chapter 14. Unused Interface Terminations

    14.2 Unused Dedicated Special Purpose Pad Interfaces See the Unused SFIO (Special Function I/O) interface pins section in the design checklist attached to this design guide. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 78...

  • Page 90: Chapter 15. Design And Bring-Up Checklists

    (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 79...

  • Page 91: Chapter 16. Orin Module Pin Descriptions

    (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 80...

  • Page 92: Chapter 17. General Routing Guidelines

    Bidirectional Differential Input/Output DIFF IN Differential Input DIFF OUT Differential Output Bidirectional Input/Output Input Output Open Drain Output I/OD Bidirectional Input / Open Drain Output Power PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 81...

  • Page 93: Routing Guidelines Format

    SE and Diff impedances. Unless otherwise noted, trace impedance values are ±15%. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 82...

  • Page 94: General Pcb Routing Guidelines

    General PCB Routing Guidelines Note: The requirements detailed in the interface signal routing requirements tables must be met for all interfaces implemented or proper operation cannot be guaranteed. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 83...

  • Page 95: Common High-Speed Interface Requirements

    Keep critical high-speed traces away from other signal traces or unrelated power traces and areas or power supply components The following figures show the common high-speed interface signal routing requirements. Figure 17-2. Common Mode Choke PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 84...

  • Page 96: Test Points For High-Speed Interfaces

    Test points should be located on the existing trace (no stub).  If the test points are placed on differential signals, they should be symmetric for each P  and N signal. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 85...
  • Page 97 USB 3.2 connector itself. If possible, the antenna or USB 3.2 location can be changed to increase physical isolation. In general, doubling the distance between antenna and noise source, reduces the coupling by around 6 dB. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 86...
  • Page 98 USB 3.2 connectors. The shield must touch the USB 3.2 body in multiple points. The shield track must have number of grounding vias so that any emitted noise from the USB 3.2 connector is swiftly grounded. PRELIMINARY INFORMATION Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 87...
  • Page 99 NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this document. NVIDIA accepts no liability related to any default, damage, costs, or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this document or (ii) customer product designs.

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