Spi - Nvidia Jetson TX2 Manual

Table 69. I2C Signal Connections
Module Pin Name Type
I2C_GP0_CLK/DAT I/OD
I2C_GP1_CLK/DAT I/OD
I2C_GP2_CLK/DAT I/OD
I2C_GP3_CLK/DAT I/OD
I2C_PM_CLK/DAT I/OD
I2C_CAM_CLK/DAT I/OD
DP0_AUX_CH+/– I/OD
DP1_AUX_CH+/– I/OD
Note: If some devices require a different voltage level than others connected to the same I2C bus, level shifters are required.
1.
For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are
2.
pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers.
De-bounce
The tables below contain the allow able De-bounce settings for the various I2C Modes.
Table 70. De-bounce Settings (Fast Mode Plus, Fast Mode & Standard Mode)
I2C Mode Clock Source
Fm+ PLLP_OUT0
Fm PLLP_OUT0
Sm PLLP_OUT0
Note: Sm = Standard Mode.

12.2 SPI

Jetson TX2/TX2i brings out three of the Tegra SPI interfaces.
Table 71. SPI Pin Descriptions
Pin # Module Pin Name
E3 SPI0_CLK
F3 SPI0_CS0#
E4 SPI0_MISO
F4 SPI0_MOSI
G13 SPI1_CLK
E14 SPI1_CS0#
F14 SPI1_MISO
F13 SPI1_MOSI
H14 SPI2_CLK
G16 SPI2_CS0#
F16 SPI2_CS1#
H15 SPI2_MISO
G15 SPI2_MOSI
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Termination
1kΩ pull-ups to VDD_1V8 on the module
1kΩ pull-ups to VDD_3V3_SYS on the
module
1kΩ pull-ups to VDD_1V8 on the module
1kΩ pull-ups to VDD_1V8 on the module
1kΩ pull-ups to VDD_1V8 on the module
1kΩ pull-ups to VDD_1V8 on the module
See eDP/HDMI/DP sections for correct
termination
See eDP/HDMI/DP sections for correct
termination
Source Clock Freq
408MHz
408MHz
408MHz
Tegra Signal Usage/Description
GPIO_SEN1 SPI 0 Clock
GPIO_SEN4 SPI 0 Chip Select 0
GPIO_SEN2 SPI 0 Master In / Slave Out
GPIO_SEN3 SPI 0 Master Out / Slave In
GPIO_CAM4 SPI 1 Clock
GPIO_CAM7 SPI 1 Chip Select 0
GPIO_CAM5 SPI 1 Master In / Slave Out
GPIO_CAM6 SPI 1 Master Out / Slave In
GPIO_WAN5 SPI 2 Clock
GPIO_WAN8 SPI 2 Chip Select 0
GPIO_MDM4 SPI 2 Chip Select 1
GPIO_WAN6 SPI 2 Master In / Slave Out
GPIO_WAN7 SPI 2 Master Out / Slave In
Description
General I2C 0 Clock\Data. Connect to CLK/Data pins of 1.8V devices
General I2C 1 Clock\Data. Connect to CLK/Data pins of 3.3V devices.
General I2C 2 Clock\Data. Connect to CLK/Data pins of 1.8V devices
General I2C 3 Clock\Data. Connect to CLK/Data pins of 1.8V devices.
Power Mon. I2C Clock\Data. Connect to CLK/Data pins of 1.8V
devices
Camera I2C Clock\Data. Connect to CLK/Data pins of any 1.8V devices
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
I2C Source Divisor Sm/Fm Divisor
5 (0x04) 10 (0x9)
5 (0x4) 26 (0x19)
20 (0x13) 26 (0x19)
Usage on the Carrier
Board
Display Connector
Expansion Header
Display/Camera Conns.
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
De-bounce Value
0
5:1
7:6
7:0
7:0
Direction
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
Bidir CMOS – 1.8V
I2C SCL Freq
1016KHz
905.8KHz
816KHz
392KHz
98KHz
Pin Type
65